Saripalli; Ramesh

Patent Applications and Registrations

Patent applications and USPTO patent grants for Saripalli; Ramesh.The latest application filed is for "higher dimensional constellations and interleaving for 10gbase-t".

Company Profile

0.5.11

Saripalli; Ramesh - Aliso Viejo CA
Saripalli; Ramesh - Tucson AZ
Saripalli; Ramesh - Irvine CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Higher Dimensional Constellations And Interleaving For 10gbase-t App 20130142206 - Kota; Kishore ; et al.	2013-06-06
Pipelined clock stretching circuitry and method for I2C logic system Grant 7,818,604 - Saripalli , et al. October 19, 2	2010-10-19
High Data Rate Serial Peripheral Interface App 20090024776 - Cheung; Hugo ; et al.	2009-01-22
Method and device for providing high data rate for a serial peripheral interface Grant 7,444,440 - Cheung , et al. October 28, 2	2008-10-28
Pipelined Clock Stretching Circuitry And Method For I2c Logic System App 20080209252 - Saripalli; Ramesh ; et al.	2008-08-28
Pipelined stop, start, address byte, and data byte technique and circuit for I.sup.2C logic system Grant 7,366,809 - Saripalli , et al. April 29, 2	2008-04-29
FIFO memory data pipelining system and method for increasing I C bus speed App 20070240011 - Saripalli; Ramesh ; et al.	2007-10-11
Method and circuit for frequency synthesis using a low drift current controlled oscillator with wide output frequency range Grant 7,151,414 - Molina , et al. December 19, 2	2006-12-19
Method and circuit for frequency synthesis using a low drift current controlled oscillator with wide output frequency range App 20060164174 - Molina; Johnnie ; et al.	2006-07-27
High precision, curvature compensated bandgap reference circuit with programmable gain App 20060061412 - Molina; Johnnie ; et al.	2006-03-23
Pipelined clock stretching circuitry and method for I2C logic system App 20050268142 - Saripalli, Ramesh ; et al.	2005-12-01
Pipelined stop, start, address byte, and data byte technique and circuit for I2C logic system App 20050228915 - Saripalli, Ramesh ; et al.	2005-10-13
Method and device for providing high data rate for a serial peripheral interface App 20050010703 - Cheung, Hugo ; et al.	2005-01-13
Method and device for providing high data rate for a serial peripheral interface App 20040098519 - Cheung, Hugo ; et al.	2004-05-20
Method and device for providing high data rate for a serial peripheral interface Grant 6,715,000 - Cheung , et al. March 30, 2	2004-03-30
Method and device for providing high data rate for a serial peripheral interface App 20020133646 - Cheung, Hugo ; et al.	2002-09-19

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