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Patent applications and USPTO patent grants for Sardesai; Viraj.The latest application filed is for "middle of line structures".
Patent | Date |
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Middle of line structures Grant 10,978,566 - Zang , et al. April 13, 2 | 2021-04-13 |
Middle Of Line Structures App 20200152749 - ZANG; Hui ;   et al. | 2020-05-14 |
Middle of line structures Grant 10,580,875 - Zang , et al. | 2020-03-03 |
Middle Of Line Structures App 20190221650 - ZANG; Hui ;   et al. | 2019-07-18 |
Structure And Method For Capping Cobalt Contacts App 20180277427 - SARDESAI; Viraj ;   et al. | 2018-09-27 |
Structure and method for capping cobalt contacts Grant 10,043,708 - Sardesai , et al. August 7, 2 | 2018-08-07 |
Integrated Efuse App 20180166402 - SARDESAI; Viraj ;   et al. | 2018-06-14 |
Formation of metal resistor and e-fuse Grant 9,997,411 - Tran , et al. June 12, 2 | 2018-06-12 |
Encapsulation Of Cobalt Metallization App 20180130702 - Patil; Suraj K. ;   et al. | 2018-05-10 |
Structure And Method For Capping Cobalt Contacts App 20180130703 - SARDESAI; Viraj ;   et al. | 2018-05-10 |
Formation of metal resistor and e-fuse Grant 9,312,185 - Tran , et al. April 12, 2 | 2016-04-12 |
Formation of air-gap spacer in transistor Grant 9,305,835 - Alptekin , et al. April 5, 2 | 2016-04-05 |
Formation Of Metal Resistor And E-fuse App 20150364419 - Tran; Cung ;   et al. | 2015-12-17 |
Formation Of Metal Resistor And E-fuse App 20150325483 - Tran; Cung ;   et al. | 2015-11-12 |
Formation Of Air-gap Spacer In Transistor App 20150243544 - Alptekin; Emre ;   et al. | 2015-08-27 |
Fully encapsulated damascene gates for Gigabit DRAMs Grant 6,504,210 - Divakaruni , et al. January 7, 2 | 2003-01-07 |
Method of metal silicide formation in integrated circuit devices Grant 5,401,677 - Bailey , et al. March 28, 1 | 1995-03-28 |
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