Santos; Gregory N.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Santos; Gregory N..The latest application filed is for "hot docking drive wedge and port replicator".

Company Profile

0.16.1

Santos; Gregory N. - Cypress TX
Santos; Gregory N. - Boca Raton FL

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Hot docking drive wedge and port replicator Grant 6,990,546 - Tang , et al. January 24, 2	2006-01-24
Hot docking drive wedge and port replicator App 20040088466 - Tang, Jeffrey C. ; et al.	2004-05-06
Hot docking drive wedge and port replicator Grant 6,665,765 - Tang , et al. December 16, 2	2003-12-16
Accelerated graphics port programmable memory access arbiter Grant 6,078,338 - Horan , et al. June 20, 2	2000-06-20
Device and method for reducing power consumption within an accelerated graphics port target Grant 6,040,845 - Melo , et al. March 21, 2	2000-03-21
Graphics address remapping table entry feature flags for customizing the operation of memory pages associated with an accelerated graphics port device Grant 5,999,198 - Horan , et al. December 7, 1	1999-12-07
Generating an error signal when accessing an invalid memory page Grant 5,990,914 - Horan , et al. November 23, 1	1999-11-23
Accelerated graphics port read transaction merging Grant 5,986,677 - Jones , et al. November 16, 1	1999-11-16
Accelerated graphics port multiple entry gart cache allocation system and method Grant 5,949,436 - Horan , et al. September 7, 1	1999-09-07
Accelerated graphics port memory mapped status and control registers Grant 5,936,640 - Horan , et al. August 10, 1	1999-08-10
System and method for invalidating and updating individual GART table entries for accelerated graphics port transaction requests Grant 5,914,730 - Santos , et al. June 22, 1	1999-06-22
Valid flag for disabling allocation of accelerated graphics port memory space Grant 5,914,727 - Horan , et al. June 22, 1	1999-06-22
Apparatus and method for positively and subtractively decoding addresses on a bus Grant 5,864,688 - Santos , et al. January 26, 1	1999-01-26
Reconfigurable dual master IDE interface Grant 5,761,460 - Santos , et al. June 2, 1	1998-06-02
Bus-to-bus read prefetch logic for improving information transfers in a multi-bus information handling system (bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus) Grant 5,581,714 - Amini , et al. December 3, 1	1996-12-03
Bus-to-bus pacing logic for improving information transfers in a multi-bus information handling system Grant 5,564,026 - Amini , et al. October 8, 1	1996-10-08
Bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus Grant 5,522,050 - Amini , et al. May 28, 1	1996-05-28

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