| Patent | Date |
|---|
Electrical Overlay Measurement Methods And Structures For Wafer-to-wafer Bonding
App 20220285234 - YOKOMIZO; Ikue ; et al. | 2022-09-08 |
Three-dimensional Memory Device Including Stairless Word Line Contact Structures For And Method Of Making The Same
App 20220189872 - SANO; Michiaki ; et al. | 2022-06-16 |
Three-dimensional Memory Device With Punch-through-resistant Word Lines And Methods For Forming The Same
App 20220028879 - MOCHIZUKI; Ryo ; et al. | 2022-01-27 |
Three-dimensional memory device with composite charge storage structures and methods for forming the same
Grant 11,101,289 - Ueda , et al. August 24, 2 | 2021-08-24 |
Three-dimensional Memory Device With Composite Charge Storage Structures And Methods For Forming The Same
App 20210257378 - UEDA; Yu ; et al. | 2021-08-19 |
Spiral gas adsorption apparatus and method of using the same
Grant 10,994,239 - Sano , et al. May 4, 2 | 2021-05-04 |
Three-dimensional memory device containing a replacement buried source line and methods of making the same
Grant 10,923,496 - Mushiga , et al. February 16, 2 | 2021-02-16 |
Bonded Assembly Containing Side Bonding Structures And Methods Of Manufacturing The Same
App 20200321324 - Sano; Michiaki ; et al. | 2020-10-08 |
Bonded assembly containing side bonding structures and methods of manufacturing the same
Grant 10,797,035 - Sano , et al. October 6, 2 | 2020-10-06 |
Distortion-compensated wafer bonding method and apparatus using a temperature-controlled backside thermal expansion layer
Grant 10,790,296 - Yamaha , et al. September 29, 2 | 2020-09-29 |
Three-dimensional memory device with locally modulated threshold voltages at drain select levels and methods of making the same
Grant 10,756,106 - Nishikawa , et al. A | 2020-08-25 |
Three-dimensional Memory Device Containing A Replacement Buried Source Line And Methods Of Making The Same
App 20200219895 - MUSHIGA; Mitsuteru ; et al. | 2020-07-09 |
Three-dimensional Memory Device With Locally Modulated Threshold Voltages At Drain Select Levels And Methods Of Making The Same
App 20200168623 - NISHIKAWA; Masatoshi ; et al. | 2020-05-28 |
Three-dimensional memory device containing drain select isolation structures and on-pitch channels and methods of making the same without an etch stop layer
Grant 10,553,599 - Chen , et al. Fe | 2020-02-04 |
Multiple vertical TFT structures for a vertical bit line architecture
Grant 10,468,459 - Oda , et al. No | 2019-11-05 |
Spiral Gas Adsorption Apparatus And Method Of Using The Same
App 20190275459 - SANO; Michiaki ; et al. | 2019-09-12 |
Three-dimensional memory device containing self-aligned interlocking bonded structure and method of making the same
Grant 10,381,322 - Azuma , et al. A | 2019-08-13 |
Multiple Vertical Tft Structures For A Vertical Bit Line Architecture
App 20190198568 - Oda; Yusuke ; et al. | 2019-06-27 |
Three-dimensional devices with wedge-shaped contact region and method of making thereof
Grant 10,290,803 - Sano , et al. | 2019-05-14 |
Three-dimensional memory device having L-shaped word lines and a support structure and methods of making the same
Grant 10,217,746 - Kim , et al. Feb | 2019-02-26 |
Three-dimensional memory device containing word lines having vertical protrusion regions and methods of making the same
Grant 10,211,215 - Ishii , et al. Feb | 2019-02-19 |
Exposure focus leveling method using region-differentiated focus scan patterns
Grant 10,209,636 - Toda , et al. Feb | 2019-02-19 |
Three-dimensional memory device having L-shaped word lines and methods of making the same
Grant 10,181,442 - Watanabe , et al. Ja | 2019-01-15 |
Methods and apparatus for three-dimensional nonvolatile memory
Grant 10,115,770 - Sel , et al. October 30, 2 | 2018-10-30 |
Semiconductor device containing multilayer titanium nitride diffusion barrier and method of making thereof
Grant 10,115,735 - Amano , et al. October 30, 2 | 2018-10-30 |
Vertical field effect transistors including two-tier select gates and method of making the same
Grant 10,083,877 - Sano , et al. September 25, 2 | 2018-09-25 |
Three-dimensional memory device having select gate electrode that is thicker than word lines and method of making thereof
Grant 10,083,982 - Shigemura , et al. September 25, 2 | 2018-09-25 |
Semiconductor Device Containing Multilayer Titanium Nitride Diffusion Barrier And Method Of Making Thereof
App 20180247954 - Amano; Fumitaka ; et al. | 2018-08-30 |
Methods And Apparatus For Three-dimensional Nonvolatile Memory
App 20180247976 - Sel; Jongsun ; et al. | 2018-08-30 |
Three-dimensional Devices With Wedge-shaped Contact Region And Method Of Making Thereof
App 20180158873 - SANO; Michiaki ; et al. | 2018-06-07 |
Three-dimensional Memory Device Having Select Gate Electrode That Is Thicker Than Word Lines And Method Of Making Thereof
App 20180138194 - SHIGEMURA; Keisuke ; et al. | 2018-05-17 |
Resistive RAM including air gaps between word lines and between vertical bit lines
Grant 9,911,790 - Shimabukuro , et al. March 6, 2 | 2018-03-06 |
Set of stepped surfaces formation for a multilevel interconnect structure
Grant 9,728,499 - Shimabukuro , et al. August 8, 2 | 2017-08-08 |
Methods and apparatus for vertical bit line structures in three-dimensional nonvolatile memory
Grant 9,673,304 - Sano , et al. June 6, 2 | 2017-06-06 |
Concave word line and convex interlayer dielectric for protecting a read/write layer
Grant 9,666,799 - Yanagida , et al. May 30, 2 | 2017-05-30 |
Concave word line and convex interlayer dielectric for protecting a read/write layer
Grant 9,620,712 - Hayashi , et al. April 11, 2 | 2017-04-11 |
Multiheight contact via structures for a multilevel interconnect structure
Grant 9,601,502 - Sano , et al. March 21, 2 | 2017-03-21 |
Method of suppressing epitaxial growth in support openings and three-dimensional memory device containing non-epitaxial support pillars in the support openings
Grant 9,576,967 - Kimura , et al. February 21, 2 | 2017-02-21 |
Multiheight electrically conductive via contacts for a multilevel interconnect structure
Grant 9,524,901 - Izumi , et al. December 20, 2 | 2016-12-20 |
Multiheight Contact Via Structures For A Multilevel Interconnect Structure
App 20160322374 - SANO; Michiaki ; et al. | 2016-11-03 |
Composite contact via structure containing an upper portion which fills a cavity within a lower portion
Grant 9,437,543 - Nakada , et al. September 6, 2 | 2016-09-06 |
Multiheight electrically conductive via contacts for a multilevel interconnect structure
Grant 9,412,753 - Izumi , et al. August 9, 2 | 2016-08-09 |
Composite Contact Via Structure Containing An Upper Portion Which Fills A Cavity Within A Lower Portion
App 20160218059 - NAKADA; Akira ; et al. | 2016-07-28 |
Multiheight contact via structures for a multilevel interconnect structure
Grant 9,401,309 - Izumi , et al. July 26, 2 | 2016-07-26 |
Set Of Stepped Surfaces Formation For A Multilevel Interconnect Structure
App 20160148835 - SHIMABUKURO; Seiji ; et al. | 2016-05-26 |
Concave Word Line And Convex Interlayer Dielectric For Protecting A Read/write Layer
App 20160126455 - Hayashi; Eiji ; et al. | 2016-05-05 |
Concave Word Line And Convex Interlayer Dielectric For Protecting A Read/write Layer
App 20160126292 - Yanagida; Naohito ; et al. | 2016-05-05 |
Bottom Recess Process For An Outer Blocking Dielectric Layer Inside A Memory Opening
App 20160111439 - Tsutsumi; Masanori ; et al. | 2016-04-21 |
Bottom recess process for an outer blocking dielectric layer inside a memory opening
Grant 9,305,937 - Tsutsumi , et al. April 5, 2 | 2016-04-05 |
Multiheight Electrically Conductive Via Contacts For A Multilevel Interconnect Structure
App 20160093626 - Izumi; Keisuke ; et al. | 2016-03-31 |
Multiheight Electrically Conductive Via Contacts For A Multilevel Interconnect Structure
App 20160093524 - Izumi; Keisuke ; et al. | 2016-03-31 |
Multiheight Contact Via Structures For A Multilevel Interconnect Structure
App 20160064281 - Izumi; Keisuke ; et al. | 2016-03-03 |
Trench multilevel contact to a 3D memory array and method of making thereof
Grant 9,230,905 - Takaki , et al. January 5, 2 | 2016-01-05 |
Methods of forming sidewall gates
Grant 9,177,964 - Nakada , et al. November 3, 2 | 2015-11-03 |
Method For Forming Oxide Below Control Gate In Vertical Channel Thin Film Transistor
App 20150249143 - Sano; Michiaki ; et al. | 2015-09-03 |
Trench Multilevel Contact to a 3D Memory Array and Method of Making Thereof
App 20150194380 - Takaki; Seje ; et al. | 2015-07-09 |
Methods of Forming Sidewall Gates
App 20150162338 - Nakada; Akira ; et al. | 2015-06-11 |
Fabricating Voids Using Slurry Protect Coat Before Chemical-Mechanical Polishing
App 20110244683 - Sano; Michiaki | 2011-10-06 |
Plasma processing method
Grant 6,743,730 - Sano June 1, 2 | 2004-06-01 |
Etching apparatus
App 20030006216 - Adachi, Kenji ; et al. | 2003-01-09 |
Semiconductor memory device and manufacturing method thereof
Grant 6,483,141 - Sano November 19, 2 | 2002-11-19 |
Semiconductor Memory Device And Manufacturing Method Thereof
App 20020058379 - SANO, MICHIAKI | 2002-05-16 |
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