Sankuratri; Raghu

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sankuratri; Raghu.The latest application filed is for "system and method for a shared cache with adaptive partitioning".

Company Profile

0.10.10

Sankuratri; Raghu - San Diego CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and apparatus for a shared cache with dynamic partitioning Grant 10,089,238 - Palacharla , et al. October 2, 2	2018-10-02
System and method for a shared cache with adaptive partitioning Grant 9,734,070 - Artieri , et al. August 15, 2	2017-08-15
System And Method For A Shared Cache With Adaptive Partitioning App 20170116118 - ARTIERI; ALAIN ; et al.	2017-04-27
Method and apparatus for flexible cache partitioning by sets and ways into component caches Grant 9,612,970 - Palacharla , et al. April 4, 2	2017-04-04
Low latency synchronization scheme for mesochronous DDR system Grant 9,437,278 - Jose , et al. September 6, 2	2016-09-06
Dynamic Random Access Memory Timing Adjustments App 20160093345 - Chun; Dexter Tamio ; et al.	2016-03-31
Method and Apparatus For Flexible Cache Partitioning By Sets And Ways Into Component Caches App 20160019157 - Palacharla; Subbarao ; et al.	2016-01-21
Method And Apparatus For A Shared Cache With Dynamic Partitioning App 20160019158 - Palacharla; Subbarao ; et al.	2016-01-21
Low Latency Synchronization Scheme For Mesochronous Ddr System App 20150340078 - Jose; Edwin ; et al.	2015-11-26
Low latency synchronization scheme for mesochronous DDR system Grant 9,123,408 - Jose , et al. September 1, 2	2015-09-01
Low Latency Synchronization Scheme For Mesochronous Ddr System App 20140347941 - Jose; Edwin ; et al.	2014-11-27
Dual channel memory architecture having reduced interface pin requirements using a double data rate scheme for the address/control signals Grant 8,325,525 - Mao , et al. December 4, 2	2012-12-04
Hybrid single and dual channel DDR interface scheme by interleaving address/control signals during dual channel operation Grant 8,098,539 - Sankuratri , et al. January 17, 2	2012-01-17
Hybrid Single and Dual Channel DDR Interface Scheme by Interleaving Address/Control Signals During Dual Channel Operation App 20110055617 - Sankuratri; Raghu ; et al.	2011-03-03
Dual Channel Memory Architecture Having Reduced Interface Pin Requirements Using a Double Data Rate Scheme for the Address/Control Signals App 20100318730 - Mao; Jian ; et al.	2010-12-16
Dual channel memory architecture having a reduced interface pin requirements using a double data rate scheme for the address/control signals Grant 7,804,735 - Mao , et al. September 28, 2	2010-09-28
Dual Channel Memory Architecture Having a Reduced Interface Pin Requirements Using a Double Data Rate Scheme for the Address/Control Signals App 20090219779 - Mao; Jian ; et al.	2009-09-03
Calibrating an integrated circuit to an electronic device App 20050114725 - Patel, Jagrut V. ; et al.	2005-05-26
Mobile communication device having dual micro processor architecture with shared digital signal processor and shared memory Grant 6,754,509 - Khan , et al. June 22, 2	2004-06-22
Method and apparatus for activating a high frequency clock following a sleep mode within a mobile station operating in a slotted paging mode Grant 6,735,454 - Yu , et al. May 11, 2	2004-05-11

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.