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Patent applications and USPTO patent grants for Sanda; Pia N.The latest application filed is for "verification of soft error resilience".
Patent | Date |
---|---|
Verification of soft error resilience Grant 8,555,234 - Tremaine , et al. October 8, 2 | 2013-10-08 |
Modeling system-level effects of soft errors Grant 8,091,050 - Bose , et al. January 3, 2 | 2012-01-03 |
Verification of Soft Error Resilience App 20110055777 - Tremaine; Robert Brett ;   et al. | 2011-03-03 |
Modeling System-Level Effects of Soft Errors App 20100083203 - Bose; Pradip ;   et al. | 2010-04-01 |
Method for VLSI system debug and timing analysis Grant 7,114,136 - Chase , et al. September 26, 2 | 2006-09-26 |
Method for VLSI system debug and timing analysis App 20050262454 - Chase, Harold W. ;   et al. | 2005-11-24 |
System and method for VLSI visualization Grant 6,895,372 - Knebel , et al. May 17, 2 | 2005-05-17 |
Geometric autogeneration of"hard"phase-shift designs for VLSI Grant 5,636,131 - Liebmann , et al. June 3, 1 | 1997-06-03 |
Geometric autogeneration of "hard" phase-shift designs for VLSI Grant 5,537,648 - Liebmann , et al. July 16, 1 | 1996-07-16 |
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