loadpatents
name:-0.30356907844543
name:-0.055673122406006
name:-0.00053000450134277
Sample; Stephen P. Patent Filings

Sample; Stephen P.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sample; Stephen P..The latest application filed is for "emulation system with time-multiplexed interconnect".

Company Profile
0.32.7
  • Sample; Stephen P. - Saratoga CA
  • Sample; Stephen P. - Mountain View CA
  • Sample; Stephen P. - Los Altos CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Emulation system with time-multiplexed interconnect
Grant 7,739,097 - Sample , et al. June 15, 2
2010-06-15
High-performance programmable logic architecture
Grant 6,882,176 - Norman , et al. April 19, 2
2005-04-19
Apparatus for emulation of electronic systems
Grant 6,842,729 - Sample , et al. January 11, 2
2005-01-11
Memory circuit for use in hardware emulation system
Grant 6,732,068 - Sample , et al. May 4, 2
2004-05-04
Method and apparatus for dynamically testing electrical interconnect
Grant 6,694,464 - Quayle , et al. February 17, 2
2004-02-17
Optimized emulation and prototyping architecture
Grant 6,625,793 - Sample , et al. September 23, 2
2003-09-23
Method for designing large standard-cell base integrated circuits
Grant 6,567,967 - Greidinger , et al. May 20, 2
2003-05-20
Emulation system with time-multiplexed interconnect
App 20030074178 - Sample, Stephen P. ;   et al.
2003-04-17
Distributed logic analyzer for use in a hardware logic emulation system
App 20020177990 - Sample, Stephen P.
2002-11-28
Memory circuit for use in hardware emulation system
App 20020161568 - Sample, Stephen P. ;   et al.
2002-10-31
Apparatus for emulation of electponic hardware system specification
App 20020107682 - Sample, Stephen P. ;   et al.
2002-08-08
Optimized emulation and prototyping architecture
App 20020095649 - Sample, Stephen P. ;   et al.
2002-07-18
Method for designing large standard-cell based integrated circuits
App 20020087940 - Greidinger, Yaacov I. ;   et al.
2002-07-04
Method for designing large standard-cell based integrated circuits
App 20020087939 - Greidinger, Yaacov I. ;   et al.
2002-07-04
Apparatus for emulation of electronic hardware system
Grant 6,377,911 - Sample , et al. April 23, 2
2002-04-23
Emulation system with time-multiplexed interconnect
Grant 6,377,912 - Sample , et al. April 23, 2
2002-04-23
PLD with on-chip memory having a shadow register
Grant 6,353,552 - Sample , et al. March 5, 2
2002-03-05
Optimized emulation and prototyping architecture
Grant 6,289,494 - Sample , et al. September 11, 2
2001-09-11
I/O buffer circuit with pin multiplexing
Grant 6,285,211 - Sample , et al. September 4, 2
2001-09-04
Programmable logic device with multi-port memory
Grant 6,219,284 - Sample , et al. April 17, 2
2001-04-17
Look-up table based logic element with complete permutability of the inputs to the secondary signals
Grant 6,184,707 - Norman , et al. February 6, 2
2001-02-06
Method and apparatus for design verification using emulation and simulation
Grant 6,058,492 - Sample , et al. May 2, 2
2000-05-02
I/O buffer circuit with pin multiplexing
Grant 6,020,760 - Sample , et al. February 1, 2
2000-02-01
Programmable logic device with multi-port memory
Grant 6,011,744 - Sample , et al. January 4, 2
2000-01-04
Hardware logic emulation system
Grant 5,963,735 - Sample , et al. October 5, 1
1999-10-05
Emulation system with time-multiplexed interconnect
Grant 5,960,191 - Sample , et al. September 28, 1
1999-09-28
Distributed logic analyzer for use in a hardware logic emulation system
Grant 5,943,490 - Sample August 24, 1
1999-08-24
Switching midplane and interconnecting system for interconnecting large numbers of signals
Grant 5,887,158 - Sample , et al. March 23, 1
1999-03-23
Diagnostic interface system for programmable logic system development
Grant 5,870,410 - Norman , et al. February 9, 1
1999-02-09
Method and apparatus for design verification using emulation and simulation
Grant 5,841,967 - Sample , et al. November 24, 1
1998-11-24
Look-up table based logic element with complete permutability of the inputs to the secondary signals
Grant 5,821,773 - Norman , et al. October 13, 1
1998-10-13
Hardware logic emulation system capable of probing internal nodes in a circuit design undergoing emulation
Grant 5,644,515 - Sample , et al. July 1, 1
1997-07-01
Method for emulating a circuit design using an electrically reconfigurable hardware emulation apparatus
Grant 5,477,475 - Sample , et al. December 19, 1
1995-12-19
Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system
Grant 5,452,239 - Dai , et al. September 19, 1
1995-09-19
Switching midplane and interconnection system for interconnecting large numbers of signals
Grant 5,352,123 - Sample , et al. October 4, 1
1994-10-04
Reconfigurable hardware emulation system
Grant 5,329,470 - Sample , et al. * July 12, 1
1994-07-12
Multiple connector arrangement for printed circuit board interconnection
Grant 5,114,353 - Sample May 19, 1
1992-05-19
Apparatus for emulation of electronic hardware system
Grant 5,109,353 - Sample , et al. April 28, 1
1992-04-28
Slave microprocessor for operation with a master microprocessor and a direct memory access controller
Grant 4,099,236 - Goodman , et al. July 4, 1
1978-07-04

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2025 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed