Samanta; Dhabalendu

Patent Applications and Registrations

Patent applications and USPTO patent grants for Samanta; Dhabalendu.The latest application filed is for "mapping programmable logic devices".

Company Profile

0.5.5

Samanta; Dhabalendu - Delhi IN
Samanta; Dhabalendu - Mayur Vihar Phase - I IN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Mapping programmable logic devices Grant 8,028,262 - Tomar , et al. September 27, 2	2011-09-27
Efficient method for mapping a logic design on field programmable gate arrays Grant 7,676,782 - Samanta , et al. March 9, 2	2010-03-09
Mapping Programmable Logic Devices App 20080209385 - Tomar; Ajay ; et al.	2008-08-28
Optimal mapping of LUT based FPGA Grant 7,415,681 - Tomar , et al. August 19, 2	2008-08-19
Method for mapping a logic circuit to a programmable look up table (LUT) Grant 7,191,427 - Sharma , et al. March 13, 2	2007-03-13
Method for finding maximum volume and minimum cut in a network of interconnected nodes Grant 7,188,328 - Sharma , et al. March 6, 2	2007-03-06
Efficient method for mapping a logic design on field programmable gate arrays App 20060190906 - Samanta; Dhabalendu ; et al.	2006-08-24
Method for finding maximum volume and minimum cut in a network of interconnected nodes App 20050235236 - Sharma, Sunil Kumar ; et al.	2005-10-20
Optimal mapping of LUT based FPGA App 20050156626 - Tomar, Ajay ; et al.	2005-07-21
Method for mapping a logic circuit to a programmable look up table (LUT) App 20050039157 - Sharma, Sunil Kumar ; et al.	2005-02-17

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