Samachisa; George

Patent Applications and Registrations

Patent applications and USPTO patent grants for Samachisa; George.The latest application filed is for "thin-film storage transistor with ferroelectric storage layer".

Company Profile

3.88.73

Samachisa; George - Atherton CA
Samachisa; George - San Jose CA
Samachisa; George - Milpitas CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Thin-film Storage Transistor With Ferroelectric Storage Layer App 20220173251 - Samachisa; George ; et al.	2022-06-02
Silicon Oxide Nitride Tunnel Dielectric For A Storage Transistor In A 3-dimensional Nor Memory String Array App 20220028871 - Herner; Scott Brad ; et al.	2022-01-27
Cool Electron Erasing In Thin-film Storage Transistors App 20210226071 - Salahuddin; Sayeef ; et al.	2021-07-22
Device structure for a 3-dimensional NOR memory array and methods for improved erase operations applied thereto Grant 11,069,696 - Harari , et al. July 20, 2	2021-07-20
Reverse memory cell Grant 10,896,916 - Harari , et al. January 19, 2	2021-01-19
Device Structure for a 3-Dimensional NOR Memory Array and Methods for Improved Erase Operations Applied Thereto App 20200051990 - Harari; Eli ; et al.	2020-02-13
Reverse Memory Cell App 20190157296 - Harari; Eli ; et al.	2019-05-23
Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture Grant 9,721,653 - Yan , et al. August 1, 2	2017-08-01
Operation modes for an inverted NAND architecture Grant 9,672,916 - Zhang , et al. June 6, 2	2017-06-06
Three-Dimensional Array of Re-Programmable Non-Volatile Memory Elements Having Vertical Bit Lines and a Single-Sided Word Line Architecture App 20170004881 - Yan; Tianhong ; et al.	2017-01-05
Operation Modes For An Inverted Nand Architecture App 20160211023 - Zhang; Yanli ; et al.	2016-07-21
Nanodot enhanced hybrid floating gate for non-volatile memory devices Grant 9,331,181 - Lee , et al. May 3, 2	2016-05-03
Operation modes for an inverted NAND architecture Grant 9,330,763 - Zhang , et al. May 3, 2	2016-05-03
Three-dimensional Array Of Re-programmable Non-volatile Memory Elements Having Vertical Bit Lines App 20160072058 - Samachisa; George	2016-03-10
Method for non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines Grant 9,245,629 - Samachisa , et al. January 26, 2	2016-01-26
Shared-gate vertical-TFT for vertical bit line array Grant 9,236,122 - Yan , et al. January 12, 2	2016-01-12
Memories with cylindrical read/write stacks Grant 9,227,456 - Chien , et al. January 5, 2	2016-01-05
Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture Grant 9,190,134 - Samachisa November 17, 2	2015-11-17
Three dimensional NAND device with silicide containing floating gates and method of making thereof Grant 9,165,940 - Chien , et al. October 20, 2	2015-10-20
Non-volatile memory having 3D array architecture with staircase word lines and vertical bit lines and methods thereof Grant 9,147,439 - Cernea , et al. September 29, 2	2015-09-29
3D non-volatile memory having low-current cells and methods Grant 9,064,547 - Cernea , et al. June 23, 2	2015-06-23
Temperature compensation of conductive bridge memory arrays Grant 9,047,983 - Scheuerlein , et al. June 2, 2	2015-06-02
Non-volatile memory structure containing nanodots and continuous metal layer charge traps and method of making thereof Grant 9,029,936 - Purayath , et al. May 12, 2	2015-05-12
Three Dimensional Nand Device With Silicide Containing Floating Gates And Method Of Making Thereof App 20150072488 - Chien; Henry ; et al.	2015-03-12
Non-volatile memory having 3D array of read/write elements with vertical bit lines and select devices and methods thereof Grant 8,958,228 - Samachisa , et al. February 17, 2	2015-02-17
Shared-gate Vertical-tft For Vertical Bit Line Array App 20150036414 - Yan; Tianhong ; et al.	2015-02-05
Three dimensional NAND device with silicide containing floating gates Grant 8,928,061 - Chien , et al. January 6, 2	2015-01-06
Non-volatile Memory Having 3d Array Of Read/write Elements With Vertical Bit Lines And Select Devices And Methods Thereof App 20140335671 - Samachisa; George ; et al.	2014-11-13
3D Non-Volatile Memory Having Low-Current Cells and Methods App 20140254231 - Cernea; Raul Adrian ; et al.	2014-09-11
Nanodot-Enhanced Hybrid Floating Gate for Non-Volatile Memory Devices App 20140252447 - Lee; Donovan ; et al.	2014-09-11
Non-volatile memory having 3D array of read/write elements with vertical bit lines and select devices and methods thereof Grant 8,824,183 - Samachisa , et al. September 2, 2	2014-09-02
NAND memory device containing nanodots and method of making thereof Grant 8,822,288 - Purayath , et al. September 2, 2	2014-09-02
Non-volatile memory having 3D array of read/write elements and read/write circuits and method thereof Grant 8,824,191 - Samachisa , et al. September 2, 2	2014-09-02
Non-volatile memory having 3D array of read/write elements with low current structures and methods thereof Grant 8,817,514 - Samachisa , et al. August 26, 2	2014-08-26
Temperature Compensation Of Conductive Bridge Memory Arrays App 20140226393 - Scheuerlein; Roy E. ; et al.	2014-08-14
Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture Grant 8,780,605 - Yan , et al. July 15, 2	2014-07-15
Three-Dimensional Array of Re-Programmable Non-Volatile Memory Elements Having Vertical Bit Lines and a Single-Sided Word Line Architecture App 20140192595 - Samachisa; George	2014-07-10
Method of making an ultrahigh density vertical NAND memory device with shielding wings Grant 8,765,543 - Alsmeier , et al. July 1, 2	2014-07-01
Three Dimensional Nand Device With Silicide Containing Floating Gates And Method Of Making Thereof App 20140175530 - Chien; Henry ; et al.	2014-06-26
Non-volatile Memory Having 3d Array Of Read/write Elements With Low Current Structures And Methods Thereof App 20140179068 - Samachisa; George ; et al.	2014-06-26
Temperature compensation of conductive bridge memory arrays Grant 8,750,066 - Scheuerlein , et al. June 10, 2	2014-06-10
Method For Non-Volatile Memory Having 3D Array of Read/Write Elements with Efficient Decoding of Vertical Bit Lines and Word Lines App 20140043911 - Samachisa; George ; et al.	2014-02-13
Ultrahigh Density Vertical Nand Memory Device And Method Of Making Thereof App 20140045307 - Alsmeier; Johann ; et al.	2014-02-13
Temperature Compensation Of Conductive Bridge Memory Arrays App 20140029356 - Scheuerlein; Roy E. ; et al.	2014-01-30
Non-volatile Memory Having 3d Array Of Read/write Elements And Read/write Circuits And Method Thereof App 20140022848 - Samachisa; George ; et al.	2014-01-23
Non-volatile memory having 3D array of read/write elements with low current structures and methods thereof Grant 8,625,322 - Samachisa , et al. January 7, 2	2014-01-07
Non-Volatile Memory Structure Containing Nanodots and Continuous Metal Layer Charge Traps and Method of Making Thereof App 20140001535 - Purayath; Vinod ; et al.	2014-01-02
NAND Memory Device Containing Nanodots and Method of Making Thereof App 20140001533 - Purayath; Vinod ; et al.	2014-01-02
Non-volatile Memory Having 3d Array Architecture With Staircase Word Lines And Vertical Bit Lines And Methods Thereof App 20130336038 - Cernea; Raul Adrian ; et al.	2013-12-19
Method of making ultrahigh density vertical NAND memory device Grant 8,580,639 - Alsmeier , et al. November 12, 2	2013-11-12
Temperature compensation of conductive bridge memory arrays Grant 8,576,651 - Scheuerlein , et al. November 5, 2	2013-11-05
Punch-through diode steering element Grant 8,575,715 - Mihnea , et al. November 5, 2	2013-11-05
Non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines Grant 8,547,720 - Samachisa , et al. October 1, 2	2013-10-01
Ultrahigh Density Vertical Nand Memory Device And Method Of Making Thereof App 20130237024 - Alsmeier; Johann ; et al.	2013-09-12
Memories with Cylindrical Read/Write Stacks App 20130229846 - Chien; Henry ; et al.	2013-09-05
Non-volatile memory having 3D array of read/write elements and read/write circuits and method thereof Grant 8,526,237 - Samachisa , et al. September 3, 2	2013-09-03
Composition of memory cell with resistance-switching layers Grant 8,520,424 - Kreupl , et al. August 27, 2	2013-08-27
Temperature Compensation Of Conductive Bridge Memory Arrays App 20130188431 - Scheuerlein; Roy E. ; et al.	2013-07-25
Memory system with reversible resistivity-switching using pulses of alternatrie polarity Grant 8,462,580 - Rabkin , et al. June 11, 2	2013-06-11
Method of making ultrahigh density vertical NAND memory device Grant 8,461,000 - Alsmeier , et al. June 11, 2	2013-06-11
Three-dimensional Array Of Re-programmable Non-volatile Memory Elements Having Vertical Bit Lines And A Single-sided Word Line Architecture App 20130121078 - Yan; Tianhong ; et al.	2013-05-16
Ultrahigh Density Vertical Nand Memory Device And Method Of Making Thereof App 20130095646 - Alsmeier; Johann ; et al.	2013-04-18
Junctionless TFT NAND flash memory Grant 8,395,942 - Samachisa , et al. March 12, 2	2013-03-12
Memory system with reversible resistivity-switching using pulses of alternate polarity Grant 8,355,271 - Rabkin , et al. January 15, 2	2013-01-15
Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture Grant 8,351,236 - Yan , et al. January 8, 2	2013-01-08
Ultrahigh density monolithic, three dimensional vertical NAND memory device Grant 8,349,681 - Alsmeier , et al. January 8, 2	2013-01-08
Transistor driven 3D memory Grant 8,351,243 - Mihnea , et al. January 8, 2	2013-01-08
Punch-through Diode Steering Element App 20120302029 - Mihnea; Andrei ; et al.	2012-11-29
Punch-through diode steering element Grant 8,274,130 - Mihnea , et al. September 25, 2	2012-09-25
Non-Volatile Memory Having 3d Array of Read/Write Elements with Low Current Structures and Methods Thereof App 20120147649 - Samachisa; George ; et al.	2012-06-14
Non-Volatile Memory Having 3D Array of Read/Write Elements with Vertical Bit Lines and Select Devices and Methods Thereof App 20120147650 - Samachisa; George ; et al.	2012-06-14
Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a double-global-bit-line architecture Grant 8,199,576 - Fasoli , et al. June 12, 2	2012-06-12
Transistor Driven 3D Memory App 20120120709 - Mihnea; Andrei ; et al.	2012-05-17
Memory System With Reversible Resistivity-switching Using Pulses Of Alternatrie Polarity App 20120120710 - Rabkin; Peter ; et al.	2012-05-17
Memory System With Reversible Resistivity-switching Using Pulses Of Alternatrie Polarity App 20120120711 - Rabkin; Peter ; et al.	2012-05-17
Ultrahigh Density Vertical Nand Memory Device & Method Of Making Thereof App 20120001249 - Alsmeier; Johann ; et al.	2012-01-05
Composition Of Memory Cell With Resistance-Switching Layers App 20110310655 - Kreupl; Franz ; et al.	2011-12-22
Non-Volatile Memory Having 3d Array of Read/Write Elements with Vertical Bit Lines and Laterally Aligned Active Elements and Methods Thereof App 20110297912 - Samachisa; George ; et al.	2011-12-08
Non-Volatile Memory Having 3d Array of Read/Write Elements and Read/Write Circuits and Method Thereof App 20110299340 - Samachisa; George ; et al.	2011-12-08
Non-Volatile Memory Having 3d Array of Read/Write Elements with Efficient Decoding of Vertical Bit Lines and Word Lines App 20110299314 - Samachisa; George ; et al.	2011-12-08
Junctionless Tft Nand Flash Memory App 20110280076 - Samachisa; George ; et al.	2011-11-17
Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines Grant 7,983,065 - Samachisa July 19, 2	2011-07-19
Methods of making flash memory cell arrays having dual control gates per memory cell charge storage element Grant 7,951,669 - Harari , et al. May 31, 2	2011-05-31
Punch-through Diode Steering Element App 20110089391 - Mihnea; Andrei ; et al.	2011-04-21
Scalable self-aligned dual floating gate memory cell array and methods of forming the array Grant 7,858,472 - Yuan , et al. December 28, 2	2010-12-28
Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements Grant 7,834,392 - Harari , et al. November 16, 2	2010-11-16
Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same Grant 7,830,698 - Chen , et al. November 9, 2	2010-11-09
Three-Dimensional Array of Re-Programmable Non-Volatile Memory Elements Having Vertical Bit Lines App 20100259960 - Samachisa; George	2010-10-14
Three-Dimensional Array of Re-Programmable Non-Volatile Memory Elements Having Vertical Bit Lines and a Single-Sided Word Line Architecture App 20100259962 - Yan; Tianhong ; et al.	2010-10-14
Three-Dimensional Array of Re-Programmable Non-Volatile Memory Elements Having Vertical Bit Lines and a Double-Global-Bit-Line Architecture App 20100259961 - Fasoli; Luca ; et al.	2010-10-14
Multi-State Non-Volatile Integrated Circuit Memory Systems that Employ Dielectric Storage Elements App 20090286370 - Harari; Eliyahou ; et al.	2009-11-19
Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same App 20090257265 - Chen; Xiying ; et al.	2009-10-15
Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements Grant 7,579,247 - Harari , et al. August 25, 2	2009-08-25
Non-volatile memory cells utilizing substrate trenches Grant 7,491,999 - Harari , et al. February 17, 2	2009-02-17
Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements Grant 7,479,677 - Harari , et al. January 20, 2	2009-01-20
Method of reducing disturbs in non-volatile memory Grant 7,468,915 - Guterman , et al. December 23, 2	2008-12-23
Substrate electron injection techniques for programming non-volatile charge storage memory cells and for controlling program disturb Grant 7,443,736 - Samachisa October 28, 2	2008-10-28
Multi-State Non-Volatile Integrated Circuit Memory Systems that Employ Dielectric Storage Elements App 20080116509 - Harari; Eliyahou ; et al.	2008-05-22
Multi-State Non-Volatile Integrated Circuit Memory Systems that Employ Dielectric Storage Elements App 20080119026 - Harari; Eliyahou ; et al.	2008-05-22
Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements Grant 7,341,918 - Harari , et al. March 11, 2	2008-03-11
Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements Grant 7,342,279 - Harari , et al. March 11, 2	2008-03-11
Highly dense monolithic three dimensional memory array and method for forming App 20080017890 - Yuan; Jack ; et al.	2008-01-24
Methods of Making Flash Memory Cell Arrays Having Dual Control Gates Per Memory Cell Charge Storage Element App 20070243680 - Harari; Eliyahou ; et al.	2007-10-18
Substrate Electron Injection Techniques for Programming Non-Volatile Charge Storage Memory Cells App 20070217264 - Samachisa; George	2007-09-20
Scalable Self-Aligned Dual Floating Gate Memory Cell Array And Methods Of Forming The Array App 20070161191 - Yuan; Jack H. ; et al.	2007-07-12
Substrate electron injection techniques for programming non-volatile charge storage memory cells Grant 7,230,847 - Samachisa June 12, 2	2007-06-12
Scalable self-aligned dual floating gate memory cell array and methods of forming the array Grant 7,211,866 - Yuan , et al. May 1, 2	2007-05-01
Method of Reducing Disturbs in Non-Volatile Memory App 20070076510 - Mangan; John S. ; et al.	2007-04-05
Method of reducing disturbs in non-volatile memory Grant 7,145,804 - Guterman , et al. December 5, 2	2006-12-05
Non-Volatile Memory Cells Utilizing Substrate Trenches App 20060227620 - Harari; Eliyahou ; et al.	2006-10-12
Non-volatile memory cells utilizing substrate trenches Grant 7,087,951 - Harari , et al. August 8, 2	2006-08-08
Substrate electron injection techniques for programming non-volatile charge storage memory cells App 20060139998 - Samachisa; George	2006-06-29
Method of reducing disturbs in non-volatile memory App 20060023507 - Mangan; John S. ; et al.	2006-02-02
Substrate electron injection techniques for programming non-volatile charge storage memory cells Grant 6,980,471 - Samachisa December 27, 2	2005-12-27
Method of reducing disturbs in non-volatile memory Grant 6,977,844 - Guterman , et al. December 20, 2	2005-12-20
Scalable self-aligned dual floating gate memory cell array and methods of forming the array Grant 6,953,970 - Yuan , et al. October 11, 2	2005-10-11
Scalable self-aligned dual floating gate memory cell array and methods of forming the array App 20050201154 - Yuan, Jack H. ; et al.	2005-09-15
Non-volatile memory cells utilizing substrate trenches Grant 6,936,887 - Harari , et al. August 30, 2	2005-08-30
Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements App 20050180210 - Harari, Eliyahou ; et al.	2005-08-18
Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements Grant 6,925,007 - Harari , et al. August 2, 2	2005-08-02
Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements App 20050157551 - Harari, Eliyahou ; et al.	2005-07-21
Method of reducing disturbs in non-volatile memory App 20050146933 - Guterman, Daniel C. ; et al.	2005-07-07
Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements Grant 6,897,522 - Harari , et al. May 24, 2	2005-05-24
Floating gate memory cells utilizing substrate trenches to scale down their size Grant 6,894,343 - Harari , et al. May 17, 2	2005-05-17
Method of reducing disturbs in non-volatile memory Grant 6,888,752 - Mangan , et al. May 3, 2	2005-05-03
Non-volatile memory cells utilizing substrate trenches App 20040212006 - Harari, Eliyahou ; et al.	2004-10-28
Scalable self-aligned dual floating gate memory cell array and methods of forming the array App 20040175888 - Yuan, Jack H. ; et al.	2004-09-09
Scalable self-aligned dual floating gate memory cell array and methods of forming the array Grant 6,762,092 - Yuan , et al. July 13, 2	2004-07-13
Scalable Self-aligned Dual Floating Gate Memory Cell Array And Methods Of Forming The Array App 20040095797 - Yuan, Jack H. ; et al.	2004-05-20
Method of reducing disturbs in non-volatile memory Grant 6,717,851 - Mangan , et al. April 6, 2	2004-04-06
Method of reducing disturbs in non-volatile memory App 20040027865 - Mangan, John S. ; et al.	2004-02-12
Non-volatile memory cells utilizing substrate trenches App 20040000688 - Harari, Eliyahou ; et al.	2004-01-01
Floating gate memory cells utilizing substrate trenches to scale down their size App 20030209751 - Harari, Eliyahou ; et al.	2003-11-13
Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements App 20030109093 - Harari, Eliyahou ; et al.	2003-06-12
Method of reducing disturbs in non-volatile memory Grant 6,570,785 - Mangan , et al. May 27, 2	2003-05-27
Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements App 20030080370 - Harari, Eliyahou ; et al.	2003-05-01
Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements App 20030082871 - Harari, Eliyahou ; et al.	2003-05-01
Steering gate and bit line segmentation in non-volatile memories Grant 6,532,172 - Harari , et al. March 11, 2	2003-03-11
Steering Gate And Bit Line Segmentation In Non-volatile Memories App 20020181266 - Harari, Eliyahou ; et al.	2002-12-05
Method of reducing disturbs in non-volatile memory App 20020051383 - Mangan, John S. ; et al.	2002-05-02
Dual floating gate EEPROM cell array with steering gates shared by adjacent cells Grant 6,344,993 - Harari , et al. February 5, 2	2002-02-05
Dual floating gate EEPROM cell array with steering gates shared adjacent cells Grant 6,266,278 - Harari , et al. July 24, 2	2001-07-24
Dual floating gate EEPROM cell array with steering gates shared by adjacent cells Grant 6,151,248 - Harari , et al. November 21, 2	2000-11-21
Processing techniques for making a dual floating gate EEPROM cell array Grant 6,103,573 - Harari , et al. August 15, 2	2000-08-15
Memory array architecture utilizing global bit lines shared by multiple cells Grant 6,091,633 - Cernea , et al. July 18, 2	2000-07-18
Low voltage erase of a flash EEPROM system having a common erase electrode for two individual erasable sectors Grant 5,677,872 - Samachisa , et al. October 14, 1	1997-10-14
Latent defect handling in EEPROM devices Grant 5,659,550 - Mehrotra , et al. August 19, 1	1997-08-19
Low voltage erase of a flash EEPROM system having a common erase electrode for two individually erasable sectors Grant 5,579,259 - Samachisa , et al. November 26, 1	1996-11-26
Latent defect handling in EEPROM devices Grant 5,428,621 - Mehrotra , et al. June 27, 1	1995-06-27