Salter, III; Robert M.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Salter, III; Robert M..The latest application filed is for "electrical stimulation device for applying frequency and peak voltage having inverse relationship".

Company Profile

1.17.3

Salter, III; Robert M. - Saratoga CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Electrical Stimulation Device For Applying Frequency And Peak Voltage Having Inverse Relationship App 20200171305 - Young; Sam Ira ; et al.	2020-06-04
Apparatus and methods for a tamper resistant bus for secure lock bit transfer Grant 8,803,548 - Salter, III August 12, 2	2014-08-12
Apparatus And Methods For A Tamper Resistant Bus For Secure Lock Bit Transfer App 20130282943 - Salter, III; Robert M.	2013-10-24
Programming method for non-volatile memory and non-volatile memory-based programmable logic device Grant 7,623,390 - Salter, III , et al. November 24, 2	2009-11-24
Method for erasing programmable interconnect cells for field programmable gate arrays using reverse bias voltage Grant 7,593,268 - Hecht , et al. September 22, 2	2009-09-22
Volatile data storage in a non-volatile memory cell array Grant 7,573,746 - Greene , et al. August 11, 2	2009-08-11
Non-volatile memory cells in a field programmable gate array Grant 7,430,137 - Greene , et al. September 30, 2	2008-09-30
Programming method for non-volatile memory and non-volatile memory-based programmable logic device Grant 7,362,610 - Salter, III , et al. April 22, 2	2008-04-22
Volatile data storage in a non-volatile memory cell array Grant 7,301,821 - Greene , et al. November 27, 2	2007-11-27
Nonvolatile reprogrammable interconnect cell with FN tunneling device for programming and erase Grant 6,252,273 - Salter, III , et al. June 26, 2	2001-06-26
Nonvolatile reprogrammable interconnect cell with programmable buried source/drain in sense transistor Grant 6,137,728 - Peng , et al. October 24, 2	2000-10-24
Nonvolatile reprogrammable interconnect cell with programmable buried bitline Grant 6,072,720 - Peng , et al. June 6, 2	2000-06-06
Nonvolatile reprogrammable interconnect cell with FN tunneling in sense Grant 5,838,040 - Salter, III , et al. November 17, 1	1998-11-17
Non-volatile memory control and data loading architecture for multiple chip processor Grant 5,623,686 - Hall , et al. April 22, 1	1997-04-22
Multiple chip package processor having feed through paths on one die Grant 5,606,710 - Hall , et al. February 25, 1	1997-02-25
Multiple chip processor architecture with memory interface control register for in-system programming Grant 5,581,779 - Hall , et al. December 3, 1	1996-12-03
In-system programming architecture for a multiple chip processor Grant 5,566,344 - Hall , et al. October 15, 1	1996-10-15
Column selector circuit for shared column CMOS EPROM Grant 5,359,555 - Salter, III October 25, 1	1994-10-25

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