Salowe; Jeffrey S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Salowe; Jeffrey S..The latest application filed is for "methods, systems, and articles of manufacture for implementing high current carrying interconnects in electronic designs".

Company Profile

0.16.1

Salowe; Jeffrey S. - Los Gatos CA
Salowe; Jeffrey S. - San Jose CA
Salowe; Jeffrey S. - Cupertino CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods, systems, and articles of manufacture for interactively implementing physical electronic designs with track patterns Grant 10,049,175 - Salowe , et al. August 14, 2	2018-08-14
Methods, systems, and articles of manufacture for implementing high current carrying interconnects in electronic designs Grant 9,817,941 - Salowe , et al. November 14, 2	2017-11-14
Methods, systems, and articles of manufacture for implementing electronic designs using constraint driven techniques Grant 9,754,072 - Salowe , et al. September 5, 2	2017-09-05
Methods, systems, and articles of manufacture for implementing electronic designs using constraint driven techniques Grant 9,384,317 - Salowe , et al. July 5, 2	2016-07-05
Methods, Systems, And Articles Of Manufacture For Implementing High Current Carrying Interconnects In Electronic Designs App 20160070841 - Salowe; Jeffrey S. ; et al.	2016-03-10
Methods, systems, and articles of manufacture for associating track patterns with rules for electronic designs Grant 9,251,299 - Salowe February 2, 2	2016-02-02
Methods, systems, and articles of manufacture for implementing electronic designs using flexible routing tracks Grant 9,213,793 - Salowe December 15, 2	2015-12-15
Methods, systems, and articles of manufacture for implementing high current carrying interconnects in electronic designs Grant 9,183,343 - Salowe , et al. November 10, 2	2015-11-10
Methods, systems, and articles of manufacture for tessellating and labeling routing space for routing electronic designs Grant 9,165,103 - Salowe October 20, 2	2015-10-20
Methods and systems for routing an electronic design using spacetiles Grant 9,075,932 - Salowe July 7, 2	2015-07-07
Methods, systems, and articles of manufacture for automatically assigning track patterns to regions for physical implementation of an electronic design Grant 8,984,465 - Salowe March 17, 2	2015-03-17
Methods, systems, and articles of manufacture for routing an electronic design using spacetiles Grant 8,935,649 - Salowe January 13, 2	2015-01-13
Method and system for visualizing pin access locations Grant 8,640,080 - Salowe , et al. January 28, 2	2014-01-28
Method and apparatus for reducing signal integrity and reliability problems in ICS through netlist changes during placement Grant 6,543,041 - Scheffer , et al. April 1, 2	2003-04-01

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