Sakanushi; Keishi

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sakanushi; Keishi.The latest application filed is for "detection method of algorithm in integrated circuit".

Company Profile

0.5.6

Sakanushi; Keishi - Kanagawa-ken JP
Sakanushi; Keishi - Osaka JP
SAKANUSHI; Keishi - Fujisawa JP
Sakanushi; Keishi - Fujisawa-shi JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Non-volatile memory device having 3D memory cell array with improved wordline and contact layout Grant 9,190,150 - Sakanushi November 17, 2	2015-11-17
Error-correcting code processing method and device Grant 9,166,624 - Imai , et al. October 20, 2	2015-10-20
Method and apparatus for generating circuit layout using design model and specification Grant 9,158,878 - Sakanushi October 13, 2	2015-10-13
Detection Method Of Algorithm In Integrated Circuit App 20150260768 - SAKANUSHI; Keishi ; et al.	2015-09-17
Design Layout Correcting Method, Recording Medium And Design Layout Correcting Apparatus App 20150074618 - Yokoyama; Yoko ; et al.	2015-03-12
Layout correcting method, recording medium and design layout correcting apparatus Grant 8,972,907 - Yokoyama , et al. March 3, 2	2015-03-03
Method For Integrated Circuit Design Layout Support By Computer And Apparatus Of Integrated Circuit Design Layout Support By Computer App 20150058816 - SAKANUSHI; Keishi	2015-02-26
Semiconductor Memory Device App 20140293700 - SAKANUSHI; Keishi	2014-10-02
Error-correcting Code Processing Method And Device App 20130061115 - Imai; Masaharu ; et al.	2013-03-07

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