Sakagami; Masahiko
Patent Applications and Registrations
Patent applications and USPTO patent grants for Sakagami; Masahiko.The latest application filed is for "semiconductor memory device".
- Sakagami; Masahiko - Kadoma JP
- Sakagami; Masahiko - Kyoto JP
- Sakagami; Masahiko - Kameoka JP
- Sakagami; Masahiko - Osaka JP
- Sakagami; Masahiko - Takatsuki JP
| Patent | Date |
|---|---|
| Semiconductor memory device Grant RE41,879 - Iwanari , et al. October 26, 2 | 2010-10-26 |
| Semiconductor memory device having a bitline amplified to a positive voltage and a negative voltage Grant 7,468,900 - Yamaoka , et al. December 23, 2 | 2008-12-23 |
| Ferroelectric memory and method for reading data from the ferroelectric memory Grant 7,307,866 - Yamaoka , et al. December 11, 2 | 2007-12-11 |
| Semiconductor memory device Grant 7,280,406 - Iwanari , et al. October 9, 2 | 2007-10-09 |
| Semiconductor memory device App 20060285378 - Yamaoka; Kunisato ; et al. | 2006-12-21 |
| Semiconductor storage device Grant 7,136,313 - Murakuki , et al. November 14, 2 | 2006-11-14 |
| Semiconductor memory device App 20060171246 - Iwanari; Shunichi ; et al. | 2006-08-03 |
| Semiconductor memory device Grant 7,085,148 - Iwanari , et al. August 1, 2 | 2006-08-01 |
| Semiconductor memory apparatus Grant 7,016,247 - Murakuki , et al. March 21, 2 | 2006-03-21 |
| Semiconductor storage device App 20050265090 - Murakuki, Yasuo ; et al. | 2005-12-01 |
| Ferroelectric memory and method for reading data from the ferroelectric memory App 20050259461 - Yamaoka, Kunisato ; et al. | 2005-11-24 |
| Semiconductor memory apparatus App 20050146969 - Murakuki, Yasuo ; et al. | 2005-07-07 |
| Semiconductor memory device App 20050078547 - Iwanari, Shunichi ; et al. | 2005-04-14 |
| Semiconductor device Grant 6,320,229 - Uchikoba , et al. November 20, 2 | 2001-11-20 |
| Memory control device Grant 5,233,557 - Sakagami , et al. August 3, 1 | 1993-08-03 |
| Dynamic type semiconductor memory Grant 5,227,697 - Sakagami July 13, 1 | 1993-07-13 |
| Semiconductor integrated circuit device including shift register having substantially equalized wiring between stages thereof Grant 4,821,299 - Kawai , et al. April 11, 1 | 1989-04-11 |
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