Saitoh; Toshiharu
Patent Applications and Registrations
Patent applications and USPTO patent grants for Saitoh; Toshiharu.The latest application filed is for "lssd-compatible edge-triggered shift register latch".
- Saitoh; Toshiharu - South Burlington VT
| Patent | Date |
|---|---|
| LSSD-compatible edge-triggered shift register latch Grant 7,543,203 - Ashton , et al. June 2, 2 | 2009-06-02 |
| Method for testing embedded DRAM arrays Grant 7,237,165 - Chadwick , et al. June 26, 2 | 2007-06-26 |
| Testing and repair methodology for memories having redundancy Grant 7,222,274 - Combs , et al. May 22, 2 | 2007-05-22 |
| Method for testing embedded DRAM arrays Grant 7,073,100 - Chadwick , et al. July 4, 2 | 2006-07-04 |
| Lssd-compatible Edge-triggered Shift Register Latch App 20050204244 - Ashton, Gerry ; et al. | 2005-09-15 |
| Testing And Repair Methodology For Memories Having Redundancy App 20050188287 - Combs, Michael L. ; et al. | 2005-08-25 |
| Method for testing embedded DRAM arrays App 20050088888 - Chadwick, Laura S. ; et al. | 2005-04-28 |
| Self-timed and self-tested fuse blow Grant 6,819,160 - Saitoh November 16, 2 | 2004-11-16 |
| Method for testing embedded DRAM arrays App 20040093539 - Chadwick, Laura S. ; et al. | 2004-05-13 |
| Self-timed and self-tested fuse blow App 20040090261 - Saitoh, Toshiharu | 2004-05-13 |
| Reduced-pin integrated circuit I/O test Grant 6,397,361 - Saitoh May 28, 2 | 2002-05-28 |
| Low power LSSD flip flops and a flushable single clock splitter for flip flops Grant 6,304,122 - Gregor , et al. October 16, 2 | 2001-10-16 |
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