Saikia; Jyotirmoy

Patent Applications and Registrations

Patent applications and USPTO patent grants for Saikia; Jyotirmoy.The latest application filed is for "scheme for masking output of scan chains in test circuit".

Company Profile

1.12.10

Saikia; Jyotirmoy - Bangalore IN
Saikia; Jyotirmoy - Pachatia IN
Saikia; Jyotirmoy - Mahadevapura IN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Scheme for masking output of scan chains in test circuit Grant 10,203,370 - Saikia , et al. Feb	2019-02-12
Handling of undesirable distribution of unknown values in testing of circuit using automated test equipment Grant 10,067,187 - Chandra , et al. September 4, 2	2018-09-04
Scheme for Masking Output of Scan Chains in Test Circuit App 20170131354 - Saikia; Jyotirmoy ; et al.	2017-05-11
Scheme for masking output of scan chains in test circuit Grant 9,588,179 - Saikia , et al. March 7, 2	2017-03-07
Scheme for Masking Output of Scan Chains in Test Circuit App 20160341795 - Chandra; Anshuman ; et al.	2016-11-24
Scheme for masking output of scan chains in test circuit Grant 9,417,287 - Chandra , et al. August 16, 2	2016-08-16
Test design optimizer for configurable scan architectures Grant 8,954,918 - Kapur , et al. February 10, 2	2015-02-10
Handling of Undesirable Distribution of Unknown Values in Testing of Circuit Using Automated Test Equipment App 20150025819 - Chandra; Anshuman ; et al.	2015-01-22
Scheme for Masking Output of Scan Chains in Test Circuit App 20140372822 - Saikia; Jyotirmoy ; et al.	2014-12-18
Scheme for Masking Output of Scan Chains in Test Circuit App 20140317463 - Chandra; Anshuman ; et al.	2014-10-23
Test Design Optimizer For Configurable Scan Architectures App 20140059399 - Kapur; Rohit ; et al.	2014-02-27
Test design optimizer for configurable scan architectures Grant 8,584,073 - Kapur , et al. November 12, 2	2013-11-12
Accelerating automatic test pattern generation in a multi-core computing environment via speculatively scheduled sequential multi-level parameter value optimization Grant 8,521,464 - Kumar , et al. August 27, 2	2013-08-27
Test architecture including cyclical cache chains, selective bypass scan chain segments, and blocking circuitry Grant 8,479,067 - Chandra , et al. July 2, 2	2013-07-02
Accelerating Automatic Test Pattern Generation in a Multi-Core Computing Environment via Speculatively Scheduled Sequential Multi-Level Parameter Value Optimization App 20110301907 - Kumar; Ashwin ; et al.	2011-12-08
Implementing hierarchical design-for-test logic for modular circuit design Grant 8,065,651 - Kapur , et al. November 22, 2	2011-11-22
Test Architecture Including Cyclical Cache Chains, Selective Bypass Scan Chain Segments, And Blocking Circuitry App 20110258498 - Chandra; Anshuman ; et al.	2011-10-20
Method And Apparatus For Implementing A Hierarchical Design-for-test Solution App 20100192030 - Kapur; Rohit ; et al.	2010-07-29
Test Design Optimizer For Configurable Scan Architectures App 20100017760 - Kapur; Rohit ; et al.	2010-01-21

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