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Patent applications and USPTO patent grants for Saigou; Yasuhiko.The latest application filed is for "multi-processor system for invalidating hierarchical cache".
Patent | Date |
---|---|
Multi-processor system for invalidating hierarchical cache Grant 5,287,484 - Nishii , et al. February 15, 1 | 1994-02-15 |
Static memory containing sense amp and sense amp switching circuit Grant 5,267,198 - Hatano , et al. November 30, 1 | 1993-11-30 |
Single-chip-cache-buffer for selectively writing write-back and exclusively writing data-block portions to main-memory based upon indication of bits and bit-strings respectively Grant 5,202,969 - Sato , et al. April 13, 1 | 1993-04-13 |
Static memory containing sense AMP and sense AMP switching circuit Grant 5,193,075 - Hatano , et al. March 9, 1 | 1993-03-09 |
Single chip cache with partial-write circuit for transferring a preselected portion of data between memory and buffer register Grant 5,146,573 - Sato , et al. September 8, 1 | 1992-09-08 |
Multi-processing system and cache apparatus for use in the same Grant 5,140,681 - Uchiyama , et al. August 18, 1 | 1992-08-18 |
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