Sahota; Kashmir

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sahota; Kashmir.The latest application filed is for "methods for forming a memory cell having a top oxide spacer".

Company Profile

0.15.2

Sahota; Kashmir - Fremont CA
Sahota; Kashmir - Union City CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods for forming a memory cell having a top oxide spacer Grant 8,384,146 - Fang , et al. February 26, 2	2013-02-26
Methods For Forming A Memory Cell Having A Top Oxide Spacer App 20120181601 - FANG; Shenqing ; et al.	2012-07-19
Methods for forming a memory cell having a top oxide spacer Grant 8,202,779 - Fang , et al. June 19, 2	2012-06-19
Methods For Forming A Memory Cell Having A Top Oxide Spacer App 20110233647 - FANG; Shenqing ; et al.	2011-09-29
Method for effectively removing polysilicon nodule defects Grant 7,449,413 - Achuthan , et al. November 11, 2	2008-11-11
Method for decreasing sheet resistivity variations of an interconnect metal layer Grant 7,358,191 - Achuthan , et al. April 15, 2	2008-04-15
Method for controlling poly 1 thickness and uniformity in a memory array fabrication process Grant 7,294,573 - Achuthan , et al. November 13, 2	2007-11-13
Method for reducing edge array erosion in a high-density array Grant 7,077,728 - Achuthan , et al. July 18, 2	2006-07-18
Methods for reduced trench isolation step height Grant 6,613,646 - Sahota , et al. September 2, 2	2003-09-02
Method for forming self-aligned contacts and interconnection lines using dual damascene techniques Grant 6,359,307 - Wang , et al. March 19, 2	2002-03-19
Method for removing anti-reflective coating layer using plasma etch process before contact CMP Grant 6,291,296 - Hui , et al. September 18, 2	2001-09-18
Reduction of silicon oxynitride film delamination in integrated circuit inter-level dielectrics Grant 6,133,619 - Sahota , et al. October 17, 2	2000-10-17
Scalable and reliable integrated circuit inter-level dielectric Grant 6,124,640 - Sahota , et al. September 26, 2	2000-09-26
Core array and periphery isolation technique Grant 6,004,862 - Kim , et al. December 21, 1	1999-12-21
Method and system for providing tapered shallow trench isolation structure profile Grant 5,998,301 - Pham , et al. December 7, 1	1999-12-07
Dopant-independent polysilicon plasma etch Grant 4,992,134 - Gupta , et al. February 12, 1	1991-02-12

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