Sadoughi; Sharmin

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sadoughi; Sharmin.The latest application filed is for "calibrating device performance within an integrated circuit".

Company Profile

0.12.3

Sadoughi; Sharmin - Menlo Park CA
Sadoughi; Sharmin - Cupertino CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Calibrating device performance within an integrated circuit Grant 8,653,844 - Sadoughi , et al. February 18, 2	2014-02-18
Method of product performance improvement by selective feature sizing of semiconductor devices Grant 8,302,064 - Sadoughi , et al. October 30, 2	2012-10-30
Calibrating Device Performance Within An Integrated Circuit App 20120229203 - Sadoughi; Sharmin ; et al.	2012-09-13
Integrated circuit device with stress reduction layer Grant 8,183,105 - Sadoughi May 22, 2	2012-05-22
Integrated Circuit Device With Stress Reduction Layer App 20120007188 - Sadoughi; Sharmin	2012-01-12
Integrated circuit device with stress reduction layer Grant 8,035,166 - Sadoughi October 11, 2	2011-10-11
Integrated Circuit Device With Stress Reduction Layer App 20100258877 - Sadoughi; Sharmin	2010-10-14
Techniques for improving negative bias temperature instability (NBTI) lifetime of field effect transistors Grant 7,629,653 - Sadoughi , et al. December 8, 2	2009-12-08
Techniques for improving negative bias temperature instability (NBTI) lifetime of field effect transistors Grant 7,256,087 - Sadoughi , et al. August 14, 2	2007-08-14
Semiconductor structure having alignment marks with shallow trench isolation Grant 7,192,839 - Ramkumar , et al. March 20, 2	2007-03-20
In situ deposition of a nitride layer and of an anti-reflective layer Grant 6,841,491 - Sadoughi , et al. January 11, 2	2005-01-11
Semiconductor structure having alignment marks with shallow trench isolation Grant 6,774,452 - Ramkumar , et al. August 10, 2	2004-08-10
Borderless contact architecture Grant 6,713,831 - Sadoughi , et al. March 30, 2	2004-03-30
Isolation scheme based on recessed locos using a sloped Si etch and dry field oxidation Grant 6,033,991 - Ramkumar , et al. March 7, 2	2000-03-07

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