loadpatents
name:-0.018225908279419
name:-0.020557880401611
name:-0.00046896934509277
Sachs; Howard G. Patent Filings

Sachs; Howard G.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sachs; Howard G..The latest application filed is for "minimized table lookup".

Company Profile
0.18.16
  • Sachs; Howard G. - Los Altos CA
  • Sachs; Howard G. - Santa Clara CA
  • Sachs; Howard G. - Belvedere CA
  • Sachs; Howard G. - Los Gatos CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Minimized Table Lookup
App 20080186316 - Sachs; Howard G.
2008-08-07
Vector Processor Architecture
App 20080059759 - Sachs; Howard G.
2008-03-06
Memory architecture for vector processor
App 20080059758 - Sachs; Howard G.
2008-03-06
Instructions for Vector Processor
App 20080059760 - Sachs; Howard G.
2008-03-06
Convolver Architecture for Vector Processor
App 20080059757 - Sachs; Howard G.
2008-03-06
Multi-Pipe Vector Block Matching Operations
App 20080052489 - Sachs; Howard G.
2008-02-28
Vector processor with multi-pipe vector block matching
App 20070150697 - Sachs; Howard G.
2007-06-28
Circuit group design methodologies
Grant 7,234,123 - Sachs June 19, 2
2007-06-19
Direct memory access (DMA) method and apparatus and DMA for video processing
App 20060259657 - Sachs; Howard G. ;   et al.
2006-11-16
Method and apparatus for clock synchronization between a processor and external devices
App 20060259807 - Sachs; Howard G. ;   et al.
2006-11-16
System for repair of ROM programming errors or defects
Grant 7,103,736 - Sachs September 5, 2
2006-09-05
Idle power reduction for state machines
Grant 7,058,832 - Sachs June 6, 2
2006-06-06
Instruction cache association crossbar switch
Grant 7,039,791 - Sachs , et al. May 2, 2
2006-05-02
Circuit group design methodologies
Grant 6,910,199 - Sachs June 21, 2
2005-06-21
VLIW processor and method therefor
Grant 6,892,293 - Sachs , et al. May 10, 2
2005-05-10
System for repair of ROM programming errors or defects
App 20050039071 - Sachs, Howard G.
2005-02-17
Circuit group design methodologies
App 20050028128 - Sachs, Howard G.
2005-02-03
Circuit group design methodologies
App 20050022146 - Sachs, Howard G.
2005-01-27
Instruction Cache Associative Crossbar Switch
App 20030191923 - SACHS, HOWARD G. ;   et al.
2003-10-09
General purpose state machine
App 20030140218 - Sachs, Howard G.
2003-07-24
Idle power reduction for state machines
App 20030140219 - Sachs, Howard G.
2003-07-24
Instruction cache association crossbar switch
App 20030079112 - Sachs, Howard G. ;   et al.
2003-04-24
Method and apparatus for controlling an instruction pipeline in a data processing system
Grant 6,282,635 - Sachs August 28, 2
2001-08-28
Method and apparatus for controlling an instruction pipeline in a data processing system
Grant 5,996,062 - Sachs November 30, 1
1999-11-30
Instruction cache associative crossbar switch system
Grant 5,794,003 - Sachs August 11, 1
1998-08-11
Software scheduled superscalar computer architecture
Grant 5,560,028 - Sachs , et al. September 24, 1
1996-09-24
Apparatus for obtaining data from a translation memory based on carry signal from adder
Grant 5,502,829 - Sachs March 26, 1
1996-03-26
Method and apparatus for translating virtual addresses in a data processing system having multiple instruction pipelines and separate TLB's
Grant 5,463,750 - Sachs October 31, 1
1995-10-31
Memory address translation system having modifiable and non-modifiable translation mechanisms
Grant 5,255,384 - Sachs , et al. October 19, 1
1993-10-19
Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency
Grant 5,091,846 - Sachs , et al. February 25, 1
1992-02-25
Apparatus for maintaining consistency of a cache memory with a primary memory
Grant 4,933,835 - Sachs , et al. June 12, 1
1990-06-12
Cache-MMU system
Grant 4,899,275 - Sachs , et al. February 6, 1
1990-02-06
Method and apparatus for addressing a cache memory
Grant 4,884,197 - Sachs , et al. November 28, 1
1989-11-28
Quadword boundary cache system
Grant 4,860,192 - Sachs , et al. August 22, 1
1989-08-22

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