S O I Tec Silicon On Insulator Technologies

USPTO Trademark & Patent Filings

Trademark applications and grants for S O I Tec Silicon On Insulator Technologies. S O I Tec Silicon On Insulator Technologies has 5 trademark applications. The latest application filed is for "GANOTEC"

Company Profile

S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES
S.O.I.TEC Silicon On Insulator Technologies
technologies insulator on silicon tec i o s
S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES - Bernin NY
S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES - Crolles Cedex FR
S.O.I Tec Silicon on Insulator Technologies; - Bernin FR
S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES - Chemin des Franques FR
S.O.I. TEC Silicon on Insulator Technologies - Bernin FR
S.O.I.TEC Silicon on Insulator Technologies - Bernin FR
S.O.I. Tec Silicon on Insulator Technologies - Bernin FR

Trademarks Patents

Patent Applications

Patent Application	Date
ETCHANT FOR CONTROLLED ETCHING OF GE AND GE-RICH SILICON GERMANIUM ALLOYS 20130146805 - 13/758521 Bedell; Stephen W. ; et al.	2013-06-13
THREE DIMENSIONAL STRUCTURES HAVING IMPROVED ALIGNMENTS BETWEEN LAYERS OF MICROCOMPONENTS 20130093033 - 13/195583 Castex; Arnaud ; et al.	2013-04-18
METHOD FOR TRIMMING A STRUCTURE OBTAINED BY THE ASSEMBLY OF TWO PLATES 20130078785 - 13/682009 Zussy; Marc ; et al.	2013-03-28
THREE DIMENSIONALLY INTEGRATED SEMICONDUCTOR SYSTEMS INCLUDING PHOTOACTIVE DEVICES AND SEMICONDUCTOR-ON-INSULATOR SUBSTRATES, AND METHODS OF FORMING SUCH THREE DIMENSIONALLY INTEGRATED SEMICONDUCTOR SYSTEMS 20130039615 - 13/206299 Nguyen; Bich-Yen ; et al.	2013-02-14
METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES IN 3D INTEGRATION PROCESSES USING RECOVERABLE SUBSTRATES, AND BONDED SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS 20130037960 - 13/206280 Sadaka; Mariam ; et al.	2013-02-14
Method and device for heating a layer of a plate by priming and light flow 9,196,490 - 13/127,468 Bruel November 24, 2	2015-11-24
Method for producing hybrid components 8,871,607 - 12/663,096 Signamarcheix , et al. October 28, 2	2014-10-28
Etchant for controlled etching of Ge and Ge-rich silicon germanium alloys 8,753,528 - 13/758,521 Bedell , et al. June 17, 2	2014-06-17
Etchant for controlled etching of Ge and Ge-rich silicon germanium alloys 8,753,528 - 13/758,521 Bedell , et al. June 17, 2	2014-06-17
Method for transferring a thin layer by proton exchange 8,693,835 - 12/937,945 Tauzin , et al. April 8, 2	2014-04-08

Patent Grants & Applications

Trademark Applications

Mark Image Registration \| Serial	Trademark Application Date
"GANOTEC" 3423078 79029856	GANOTEC 2006-02-02
"D-BSOI" 3223751 78316644	D-BSOI 2003-10-21
"TRACIT TECHNOLOGIES" 3031387 78287955	TRACIT TECHNOLOGIES 2003-08-15
"QUASIC" 2847218 76412119	QUASIC 2002-05-23
"SMART CUT" 2401406 75635084	SMART CUT 1999-02-04

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