Ruttloff; Kerstin

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ruttloff; Kerstin.The latest application filed is for "sacrificial spacer approach for differential source/drain implantation spacers in transistors comprising a high-k metal gate electrode structure".

Company Profile

1.17.15

Ruttloff; Kerstin - Hainichen N/A DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Multi-step deposition of a spacer material for reducing void formation in a dielectric material of a contact level of a semiconductor device Grant 8,987,103 - Lenski , et al. March 24, 2	2015-03-24
Oxide deposition by using a double liner approach for reducing pattern density dependence in sophisticated semiconductor devices Grant 8,772,843 - Kronholz , et al. July 8, 2	2014-07-08
Sacrificial spacer approach for differential source/drain implantation spacers in transistors comprising a high-k metal gate electrode structure Grant 8,709,902 - Scheiper , et al. April 29, 2	2014-04-29
Threshold adjustment for MOS devices by adapting a spacer width prior to implantation Grant 8,440,534 - Griebenow , et al. May 14, 2	2013-05-14
SOI semiconductor device comprising substrate diodes having a topography tolerant contact structure Grant 8,436,425 - Heinrich , et al. May 7, 2	2013-05-07
Contacts and vias of a semiconductor device formed by a hard mask and double exposure Grant 8,318,598 - Beyer , et al. November 27, 2	2012-11-27
Sacrificial Spacer Approach for Differential Source/Drain Implantation Spacers in Transistors Comprising a High-K Metal Gate Electrode Structure App 20120156837 - Scheiper; Thilo ; et al.	2012-06-21
Drive current adjustment for transistors by local gate engineering Grant 8,188,871 - Horstmann , et al. May 29, 2	2012-05-29
Oxide Deposition by Using a Double Liner Approach for Reducing Pattern Density Dependence in Sophisticated Semiconductor Devices App 20120049296 - Kronholz; Stephan ; et al.	2012-03-01
Method of creating a strained channel region in a transistor by deep implantation of strain-inducing species below the channel region Grant 8,110,487 - Griebenow , et al. February 7, 2	2012-02-07
Etch stop layer of reduced thickness for patterning a dielectric material in a contact level of closely spaced transistors Grant 8,097,542 - Wieczorek , et al. January 17, 2	2012-01-17
SOI semiconductor device with reduced topography above a substrate window area Grant 8,048,726 - Heinrich , et al. November 1, 2	2011-11-01
Method for reducing defects of gate of CMOS devices during cleaning processes by modifying a parasitic PN junction Grant 8,039,338 - Horstmann , et al. October 18, 2	2011-10-18
Threshold Adjustment For Mos Devices By Adapting A Spacer Width Prior To Implantation App 20110223732 - Griebenow; Uwe ; et al.	2011-09-15
Soi Semiconductor Device Comprising Substrate Diodes Having A Topography Tolerant Contact Structure App 20110186929 - Heinrich; Jens ; et al.	2011-08-04
Soi Semiconductor Device With Reduced Topography Above A Substrate Window Area App 20110189825 - Heinrich; Jens ; et al.	2011-08-04
Enhanced cap layer integrity in a high-K metal gate stack by using a hard mask for offset spacer patterning Grant 7,981,740 - Lenski , et al. July 19, 2	2011-07-19
Enhanced Cap Layer Integrity In A High-k Metal Gate Stack By Using A Hard Mask For Offset Spacer Patterning App 20100330757 - Lenski; Markus ; et al.	2010-12-30
Multi-step Deposition Of A Spacer Material For Reducing Void Formation In A Dielectric Material Of A Contact Level Of A Semiconductor Device App 20100289083 - Lenski; Markus ; et al.	2010-11-18
Contacts And Vias Of A Semiconductor Device Formed By A Hard Mask And Double Exposure App 20100078823 - Beyer; Sven ; et al.	2010-04-01
Technique For Reducing Silicide Non-uniformities In Polysilicon Gate Electrodes By An Intermediate Diffusion Blocking Layer App 20100025782 - Griebenow; Uwe ; et al.	2010-02-04
Drive Current Adjustment For Transistors By Local Gate Engineering App 20100025776 - Horstmann; Manfred ; et al.	2010-02-04
Threshold adjustment for MOS devices by adapting a spacer width prior to implantation App 20090321850 - Griebenow; Uwe ; et al.	2009-12-31
Drive Current Adjustment For Transistors Formed In The Same Active Region By Locally Inducing Different Lateral Strain Levels In The Active Region App 20090294868 - Griebenow; Uwe ; et al.	2009-12-03
Method For Reducing Defects Of Gate Of Cmos Devices During Cleaning Processes By Modifying A Parasitic Pn Junction App 20090273036 - Horstmann; Manfred ; et al.	2009-11-05
Etch Stop Layer Of Reduced Thickness For Patterning A Dielectric Material In A Contact Level Of Closely Spaced Transistors App 20090218629 - Wieczorek; Karsten ; et al.	2009-09-03
Method Of Creating A Strained Channel Region In A Transistor By Deep Implantation Of Strain-inducing Species Below The Channel Region App 20090194789 - Griebenow; Uwe ; et al.	2009-08-06

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