Rutenbar; Rob A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Rutenbar; Rob A..The latest application filed is for "method and system for modeling uncertainties in integrated circuits, systems, and fabrication processes".

Company Profile

0.13.6

Rutenbar; Rob A. - Pittsburgh PA US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Acoustic scoring unit implemented on a single FPGA or ASIC Grant 8,639,510 - Yu , et al. January 28, 2	2014-01-28
Hardware-implemented scalable modular engine for low-power speech recognition Grant 8,463,610 - Bourke , et al. June 11, 2	2013-06-11
Hardware implemented backend search engine for a high-rate speech recognition system Grant 8,352,265 - Lin , et al. January 8, 2	2013-01-08
Method and apparatus for rapidly modeling and simulating intra-die statistical variations in integrated circuits using compressed parameter models Grant 8,290,761 - Singhee , et al. October 16, 2	2012-10-16
Method and system for modeling uncertainties in integrated circuits, systems, and fabrication processes Grant 7,920,992 - Rutenbar , et al. April 5, 2	2011-04-05
Method and system for modeling uncertainties in integrated circuits, systems, and fabrication processes App 20060206294 - Rutenbar; Rob A. ; et al.	2006-09-14
Method for generating constrained component placement for integrated circuits and packages Grant 7,093,220 - Fallon , et al. August 15, 2	2006-08-15
Method for automatically sizing and biasing circuits by means of a database Grant 7,058,916 - Phelps , et al. June 6, 2	2006-06-06
Method and apparatus for quantifying tradeoffs for multiple competing goals in circuit design Grant 6,957,400 - Liu , et al. October 18, 2	2005-10-18
Method and apparatus for exact relative positioning of devices in a semiconductor circuit layout Grant 6,918,102 - Rutenbar , et al. July 12, 2	2005-07-12
Integrated circuit design layout compaction method Grant 6,874,133 - Gopalakrishnan , et al. March 29, 2	2005-03-29
Method for generating constrained component placement for integrated circuits and packages App 20050028122 - Fallon, Elias ; et al.	2005-02-03
Method and apparatus for quantifying tradeoffs for multiple competing goals in circuit design App 20040243947 - Liu, Hongzhou ; et al.	2004-12-02
Integrated circuit design layout compaction method App 20040111682 - Gopalakrishnan, Prakash ; et al.	2004-06-10
Method of creating conformal outlines for use in transistor level semiconductor layouts Grant 6,711,725 - Rutenbar , et al. March 23, 2	2004-03-23
Method and apparatus for exact relative positioning of devices in a semiconductor circuit layout App 20030131333 - Rutenbar, Rob A. ; et al.	2003-07-10
Method for automatically sizing and biasing circuits App 20030009729 - Phelps, Rodney ; et al.	2003-01-09

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