loadpatents
name:-0.009119987487793
name:-0.011406183242798
name:-0.0014679431915283
Russo; Richard F. Patent Filings

Russo; Richard F.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Russo; Richard F..The latest application filed is for "scalable interrupts".

Company Profile
2.11.9
  • Russo; Richard F. - San Jose CA
  • Russo; Richard F. - Saratoga CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Scalable Interrupts
App 20220083484 - Gonion; Jeffrey E. ;   et al.
2022-03-17
DSB Operation with Excluded Region
App 20220083338 - Gonion; Jeff ;   et al.
2022-03-17
History file for previous register mapping storage and last reference indication
Grant 11,200,062 - Duggal , et al. December 14, 2
2021-12-14
Architected state retention for a frequent operating state switching processor
Grant 10,990,159 - Semeria , et al. April 27, 2
2021-04-27
Last Physical Register Reference Scheme
App 20210064376 - Duggal; Deepankar ;   et al.
2021-03-04
Speculative writes to special-purpose register
Grant 10,838,723 - Tsay , et al. November 17, 2
2020-11-17
System and method for predicting memory dependence when a source register of a push instruction matches the destination register of a pop instruction
Grant 10,838,729 - Al-Otoom , et al. November 17, 2
2020-11-17
Processor including multiple dissimilar processor cores that implement different portions of instruction set architecture
Grant 10,401,945 - Williamson , et al. Sep
2019-09-03
Architected State Retention
App 20180307297 - Semeria; Bernard Joseph ;   et al.
2018-10-25
Processor Including Multiple Dissimilar Processor Cores that Implement Different Portions of Instruction Set Architecture
App 20180217659 - Williamson; David J. ;   et al.
2018-08-02
Execution unit power management
Grant 10,037,073 - Catovic , et al. July 31, 2
2018-07-31
Processor including multiple dissimilar processor cores that implement different portions of instruction set architecture
Grant 9,958,932 - Williamson , et al. May 1, 2
2018-05-01
Program counter capturing
Grant 9,952,863 - Blasco , et al. April 24, 2
2018-04-24
Immediate branch recode that handles aliasing
Grant 9,940,262 - Sundar , et al. April 10, 2
2018-04-10
Hardware migration between dissimilar cores
Grant 9,928,115 - Hardage, Jr. , et al. March 27, 2
2018-03-27
Hardware Migration between Dissimilar Cores
App 20170068575 - Hardage, JR.; James N. ;   et al.
2017-03-09
Mechanism for allowing speculative execution of loads beyond a wait for event instruction
Grant 9,501,284 - Kanapathipillai , et al. November 22, 2
2016-11-22
Processor Including Multiple Dissimilar Processor Cores that Implement Different Portions of Instruction Set Architecture
App 20160147290 - Williamson; David J. ;   et al.
2016-05-26
Mechanism For Allowing Speculative Execution Of Loads Beyond A Wait For Event Instruction
App 20160092236 - Kanapathipaillai; Pradeep ;   et al.
2016-03-31
Immediate Branch Recode That Handles Aliasing
App 20160085550 - Sundar; Shyam ;   et al.
2016-03-24

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