Russell; David J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Russell; David J..The latest application filed is for "interface for limiting substrate damage due to discrete failure".

Company Profile

3.53.42

Russell; David J. - Owego NY
Russell; David J. - Oswego NY
Russell; David J. - Apalachin NY US
Russell; David J - Owego NY
Russell; David J. - Owege NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Glass cloth including attached fibers Grant 10,801,137 - Chamberlin , et al. October 13, 2	2020-10-13
Reduced-warpage laminate structure Grant 10,685,919 - Lamorey , et al.	2020-06-16
Coating for limiting substrate damage due to discrete failure Grant 10,492,289 - Chamberlin , et al. Nov	2019-11-26
Coating for limiting substrate damage due to discrete failure Grant 10,470,290 - Chamberlin , et al. No	2019-11-05
Interface for limiting substrate damage due to discrete failure Grant 10,342,122 - Chamberlin , et al.	2019-07-02
Reduction of solder interconnect stress Grant 10,276,534 - Call , et al.	2019-04-30
Method of fabricating contacts of an electronic package structure to reduce solder interconnect stress Grant 10,276,535 - Call , et al.	2019-04-30
Interface for limiting substrate damage due to discrete failure Grant 10,206,278 - Chamberlain , et al. Feb	2019-02-12
Printed circuit board and methods to enhance reliability Grant 10,172,243 - Chamberlin , et al. J	2019-01-01
Interface for Limiting Substrate Damage Due to Discrete Failure App 20180332701 - Chamberlin; Bruce J. ; et al.	2018-11-15
Solder for Limiting Substrate Damage Due to Discrete Failure App 20180318968 - Chamberlin; Bruce J. ; et al.	2018-11-08
Solder for Limiting Substrate Damage Due to Discrete Failure App 20180318969 - Chamberlin; Bruce J. ; et al.	2018-11-08
Coating for Limiting Substrate Damage Due to Discrete Failure App 20180324944 - Chamberlin; Bruce J. ; et al.	2018-11-08
Coating for Limiting Substrate Damage Due to Discrete Failure App 20180324946 - Chamberlin; Bruce J. ; et al.	2018-11-08
Interface for Limiting Substrate Damage Due to Discrete Failure App 20180324945 - Chamberlin; Bruce J. ; et al.	2018-11-08
Laminate substrate thermal warpage prediction for designing a laminate substrate Grant 10,108,753 - Call , et al. October 23, 2	2018-10-23
Interface for limiting substrate damage due to discrete failure Grant 10,080,283 - Chamberlin , et al. September 18, 2	2018-09-18
Image analysis methods for plated through hole reliability Grant 9,990,707 - Czaplewski , et al. June 5, 2	2018-06-05
Printed Circuit Board And Methods To Enhance Reliability App 20180139852 - CHAMBERLIN; Bruce J. ; et al.	2018-05-17
Glass interposer with embedded thermoelectric devices Grant 9,913,405 - Gambino , et al. March 6, 2	2018-03-06
Reduction Of Solder Interconnect Stress App 20180061800 - Call; Anson J. ; et al.	2018-03-01
Reduction Of Solder Interconnect Stress App 20180061799 - Call; Anson J. ; et al.	2018-03-01
Glass Cloth Including Attached Fibers App 20180023225 - Chamberlin; Bruce J. ; et al.	2018-01-25
Reduction of solder interconnect stress Grant 9,865,557 - Call , et al. January 9, 2	2018-01-09
Laminate Substrate Thermal Warpage Prediction For Designing A Laminate Substrate App 20170351783 - Call; Anson J. ; et al.	2017-12-07
Image Analysis Methods For Plated Through Hole Reliability App 20170330316 - CZAPLEWSKI; Sarah K. ; et al.	2017-11-16
Reduced-warpage Laminate Structure App 20170148749 - Lamorey; Mark C. ; et al.	2017-05-25
Reduced-warpage laminate structure Grant 9,613,915 - Lamorey , et al. April 4, 2	2017-04-04
Method of forming a glass interposer with thermal vias Grant 9,585,257 - Gambino , et al. February 28, 2	2017-02-28
In-plane copper imbalance for warpage prediction Grant 9,563,732 - Call , et al. February 7, 2	2017-02-07
Reduced-warpage laminate structure Grant 9,543,255 - Lamorey , et al. January 10, 2	2017-01-10
Sacrificial carrier dicing of semiconductor wafers Grant 9,484,239 - Graf , et al. November 1, 2	2016-11-01
Sacrificial carrier dicing of semiconductor wafers Grant 9,478,453 - Graf , et al. October 25, 2	2016-10-25
Glass Interposer With Embedded Thermoelectric Devices App 20160286686 - Gambino; Jeffrey P. ; et al.	2016-09-29
Glass Interposer With Thermal Vias App 20160286660 - Gambino; Jeffrey P. ; et al.	2016-09-29
Dual layer stack for contact formation Grant 9,401,336 - Arvin , et al. July 26, 2	2016-07-26
Reduced-warpage Laminate Structure App 20160157357 - Lamorey; Mark C. ; et al.	2016-06-02
Reduced-warpage Laminate Structure App 20160155708 - Lamorey; Mark C. ; et al.	2016-06-02
Dual Layer Stack For Contact Formation App 20160126201 - Arvin; Charles L. ; et al.	2016-05-05
Sacrificial Carrier Dicing of Semiconductor Wafers App 20160079111 - Graf; Richard S. ; et al.	2016-03-17
Sacrificial Carrier Dicing of Semiconductor Wafers App 20160079117 - Graf; Richard S. ; et al.	2016-03-17
Under ball metallurgy (UBM) for improved electromigration Grant 9,142,501 - Arvin , et al. September 22, 2	2015-09-22
Construction of reliable stacked via in electronic substrates--vertical stiffness control method Grant 9,099,458 - Kacker , et al. August 4, 2	2015-08-04
Under Ball Metallurgy (ubm) For Improved Electromigration App 20140339699 - Arvin; Charles L. ; et al.	2014-11-20
Construction of reliable stacked via in electronic substrates--vertical stiffness control method Grant 8,866,026 - Kacker , et al. October 21, 2	2014-10-21
Underbump metallurgy employing an electrolytic Cu / electorlytic Ni / electrolytic Cu stack Grant 8,587,112 - Arvin , et al. November 19, 2	2013-11-19
Clustered stacked vias for reliable electronic substrates Grant 8,522,430 - Kacker , et al. September 3, 2	2013-09-03
Construction Of Reliable Stacked Via In Electronic Substrates - Vertical Stiffness Control Method App 20120299195 - Kacker; Karan ; et al.	2012-11-29
Clustered Stacked Vias For Reliable Electronic Substrates App 20120279061 - Kacker; Karan ; et al.	2012-11-08
Construction Of Reliable Stacked Via In Electronic Substrates - Vertical Stiffness Control Method App 20120267158 - Kacker; Karan ; et al.	2012-10-25
Construction of reliable stacked via in electronic substrates--vertical stiffness control method Grant 8,258,410 - Kacker , et al. September 4, 2	2012-09-04
Clustered stacked vias for reliable electronic substrates Grant 8,242,593 - Kacker , et al. August 14, 2	2012-08-14
UNDERBUMP METALLURGY EMPLOYING AN ELECTROLYTIC Cu / ELECTORLYTIC Ni / ELECTROLYTIC Cu STACK App 20120198692 - Arvin; Charles L. ; et al.	2012-08-09
Bump pad metallurgy employing an electrolytic Cu / electorlytic Ni / electrolytic Cu stack Grant 8,232,655 - Arvin , et al. July 31, 2	2012-07-31
Electrical Contact Alignment Posts App 20120032321 - West; David J. ; et al.	2012-02-09
Structure and method for reliability evaluation of FCPBGA substrates for high power semiconductor packaging applications Grant 7,982,475 - Russell , et al. July 19, 2	2011-07-19
Semiconductor package having non-aligned active vias Grant 7,868,459 - Audet , et al. January 11, 2	2011-01-11
Electroless Nickel Leveling Of Lga Pad Sites For High Performance Organic Lga App 20090294971 - BLACKSHEAR; Edmund D. ; et al.	2009-12-03
Organic Substrate with Asymmetric Thickness for Warp Mitigation App 20090265028 - Sri-Jayantha; Sri M. ; et al.	2009-10-22
Construction of Reliable Stacked Via in Electronic Substrates - Vertical Stiffness Control Method App 20090188705 - Kacker; Karan ; et al.	2009-07-30
Clustered Stacked Vias For Reliable Electronic Substrates App 20090189290 - Kacker; Karan ; et al.	2009-07-30
Embedded Constrainer Discs For Reliable Stacked Vias In Electronic Substrates App 20090189289 - Kacker; Karan ; et al.	2009-07-30
Bump Pad Metallurgy Employing An Electrolytic Cu / Electorlytic Ni / Electrolytic Cu Stack App 20090174045 - Arvin; Charles L. ; et al.	2009-07-09
Semiconductor Package Having Non-aligned Active Vias App 20080054482 - Audet; Jean ; et al.	2008-03-06
Enhanced via structure for organic module performance Grant 7,312,523 - Audet , et al. December 25, 2	2007-12-25
Enhanced Via Structure For Organic Module Performance App 20070023913 - Audet; Jean J. ; et al.	2007-02-01
Standoff Structures For Surface Mount Components App 20070007323 - Russell; David J. ; et al.	2007-01-11
Photoimageable dielectric epoxy resin system film Grant 6,835,533 - Foster , et al. December 28, 2	2004-12-28
Forming a through hole in a photoimageable dielectric structure Grant 6,830,875 - Fuerniss , et al. December 14, 2	2004-12-14
Photoimageable dielectric epoxy resin system film App 20040161702 - Foster, Elizabeth ; et al.	2004-08-19
Method of fabricating circuitized structures Grant 6,706,464 - Foster , et al. March 16, 2	2004-03-16
Laser ablatable material and its use Grant 6,689,543 - Kresge , et al. February 10, 2	2004-02-10
Method of fabricating circuitized structures App 20030129536 - Foster, Elizabeth ; et al.	2003-07-10
Circuitry with integrated passive components and method for producing Grant 6,542,379 - Lauffer , et al. April 1, 2	2003-04-01
Fabrication of a metalized blind via App 20030054635 - Egitto, Frank D. ; et al.	2003-03-20
Forming a through hole in a photoimageable dielectric structure App 20030047357 - Fuerniss, Stephen J. ; et al.	2003-03-13
Method of fabricating circuitized structures Grant 6,528,218 - Foster , et al. March 4, 2	2003-03-04
Printed wiring board with improved plated through hole fatigue life Grant 6,423,905 - Brodsky , et al. July 23, 2	2002-07-23
Laser ablatable material and its use App 20020094491 - Kresge, John S. ; et al.	2002-07-18
Process for manufacturing a multi-layer circuit board App 20010042733 - Appelt, Bernd K. ; et al.	2001-11-22
Method of forming a chip carrier by joining a laminate layer and stiffener App 20010018799 - Lauffer, John M. ; et al.	2001-09-06
Laminate substrate having joining layer of photoimageable material Grant 6,195,264 - Lauffer , et al. February 27, 2	2001-02-27
Interconnect structure for joining a chip to a circuit card Grant 6,121,069 - Boyko , et al. September 19, 2	2000-09-19
Sequential build-up organic chip carrier and method of manufacture Grant 6,080,668 - Lauffer , et al. June 27, 2	2000-06-27
Ball limiting metal mask and tin enrichment of high melting point solder for low temperature interconnection Grant 5,953,623 - Boyko , et al. September 14, 1	1999-09-14
Composition for photo imaging Grant 5,439,766 - Day , et al. * August 8, 1	1995-08-08
Composition for photo imaging Grant 5,304,457 - Day , et al. * April 19, 1	1994-04-19
Composition for photo imaging Grant 5,300,402 - Card, Jr. , et al. * April 5, 1	1994-04-05
Composition for photo imaging Grant 5,278,010 - Day , et al. January 11, 1	1994-01-11
Composition for photo imaging Grant 5,264,325 - Allen , et al. November 23, 1	1993-11-23
Composition for photo imaging Grant 5,026,624 - Day , et al. June 25, 1	1991-06-25