Rupp; Thomas S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Rupp; Thomas S..The latest application filed is for "method of reducing erosion of a nitride gate cap layer during reactive ion etch of nitride liner layer for bit line contact of dram device".

Company Profile

0.8.1

Rupp; Thomas S. - Faak am See AT
Rupp; Thomas S. - Stormville NY
Rupp; Thomas S. - Stomrville NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method of reducing erosion of a nitride gate cap layer during reactive ion etch of nitride liner layer for bit line contact of DRAM device Grant 6,960,523 - Maldei , et al. November 1, 2	2005-11-01
Method of reducing erosion of a nitride gate cap layer during reactive ion etch of nitride liner layer for bit line contact of DRAM device App 20040195607 - Maldei, Michael ; et al.	2004-10-07
Vertical device formed adjacent to a wordline sidewall and method for semiconductor chips Grant 6,699,750 - Rupp March 2, 2	2004-03-02
Manufacturing of cavity fuses on gate conductor level Grant 6,274,440 - Arndt , et al. August 14, 2	2001-08-14
Embedded vertical DRAM cells and dual workfunction logic gates Grant 6,258,659 - Gruening , et al. July 10, 2	2001-07-10
Contact and deep trench patterning Grant 6,204,187 - Rupp , et al. March 20, 2	2001-03-20
Semiconductor device with vertical transistor and buried word line Grant 6,172,390 - Rupp , et al. January 9, 2	2001-01-09
Vertical DRAM cell with wordline self-aligned to storage trench Grant 6,153,902 - Furukawa , et al. November 28, 2	2000-11-28
Vertical device formed adjacent to a wordline sidewall and method for semiconductor chips Grant 6,091,094 - Rupp July 18, 2	2000-07-18

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