Runnion; Edward Franklin

Patent Applications and Registrations

Patent applications and USPTO patent grants for Runnion; Edward Franklin.The latest application filed is for "applying negative gate voltage to wordlines adjacent to wordline associated with read or verify to reduce adjacent wordline disturb".

Company Profile

0.5.4

Runnion; Edward Franklin - San Jose CA
Runnion; Edward Franklin - Santa Clara CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Applying negative gate voltage to wordlines adjacent to wordline associated with read or verify to reduce adjacent wordline disturb Grant 7,995,386 - Mizuguchi , et al. August 9, 2	2011-08-09
Applying Negative Gate Voltage To Wordlines Adjacent To Wordline Associated With Read Or Verify To Reduce Adjacent Wordline Disturb App 20100128521 - Mizuguchi; Yuji ; et al.	2010-05-27
Algorithm for charge loss reduction and Vt distribution improvement Grant 7,619,932 - Jones , et al. November 17, 2	2009-11-17
Cycling improvement using higher erase bias Grant 7,561,471 - Park , et al. July 14, 2	2009-07-14
ALGORITHM FOR CHARGE LOSS REDUCTION AND Vt DISTRIBUTION IMPROVEMENT App 20090154251 - Jones; Gwyn Robert ; et al.	2009-06-18
Cycling improvement using higher erase bias App 20080151644 - Park; Sheung-Hee ; et al.	2008-06-26
Ramp Gate Erase For Dual Bit Flash Memory App 20080037330 - Park; Sheung-Hee ; et al.	2008-02-14
Ramp gate erase for dual bit flash memory Grant 7,319,615 - Park , et al. January 15, 2	2008-01-15
Memory device and methods of using negative gate stress to correct over-erased memory cells Grant 6,834,012 - He , et al. December 21, 2	2004-12-21

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