Runnion; Edward F.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Runnion; Edward F..The latest application filed is for "pocket implant for complementary bit disturb improvement and charging improvement of sonos memory cell".

Company Profile

0.8.3

Runnion; Edward F. - Santa Clara CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods and systems for reducing the threshold voltage distribution following a memory cell erase Grant 7,170,796 - He , et al. January 30, 2	2007-01-30
Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell Grant 6,958,272 - Lingunis , et al. October 25, 2	2005-10-25
Method to obtain temperature independent program threshold voltage distribution using temperature dependent voltage reference Grant 6,944,057 - Runnion , et al. September 13, 2	2005-09-13
Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell App 20050153508 - Lingunis, Emmanuil H. ; et al.	2005-07-14
Method and system for erasing a nitride memory device Grant 6,906,959 - Randolph , et al. June 14, 2	2005-06-14
Method of controlling program threshold voltage distribution of a dual cell memory device Grant 6,822,909 - Hamilton , et al. November 23, 2	2004-11-23
Pre-charge method for reading a non-volatile memory cell Grant 6,788,583 - He , et al. September 7, 2	2004-09-07
Method and system for erasing a nitride memory device App 20040169218 - Randolph, Mark W. ; et al.	2004-09-02
Method of programming a dual cell memory device Grant 6,775,187 - Hamilton , et al. August 10, 2	2004-08-10
Pre-charge Method For Reading A Non-volatile Memory Cell App 20040105312 - He, Yi ; et al.	2004-06-03
Method of improving dynamic reference tracking for flash memory unit Grant 6,735,114 - Hamilton , et al. May 11, 2	2004-05-11

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