| Patent | Date |
|---|
Fin Top Hard Mask Formation After Wafer Flipping Process
App 20220231021 - Zhang; Chen ; et al. | 2022-07-21 |
Transferrable Pillar Structure For Fanout Package Or Interconnect Bridge
App 20220181286 - Rubin; Joshua M. ; et al. | 2022-06-09 |
Precision Thin Electronics Handling Integration
App 20210366789 - Knickerbocker; John ; et al. | 2021-11-25 |
Multi-chip package structures with discrete redistribution layers
Grant 11,164,817 - Rubin , et al. November 2, 2 | 2021-11-02 |
Contact formation for stacked vertical transport field-effect transistors
Grant 11,164,791 - Wu , et al. November 2, 2 | 2021-11-02 |
Back-side Memory Element With Local Memory Select Transistor
App 20210313391 - Kumar; Arvind ; et al. | 2021-10-07 |
Multi-chip package structure having high density chip interconnect bridge with embedded power distribution network
Grant 11,133,259 - Rubin , et al. September 28, 2 | 2021-09-28 |
Reducing Gate Resistance In Stacked Vertical Transport Field Effect Transistors
App 20210280578 - WU; Heng ; et al. | 2021-09-09 |
Multi-chip package structures formed by joining chips to pre-positioned chip interconnect bridge devices
Grant 11,114,410 - Rubin , et al. September 7, 2 | 2021-09-07 |
Multi-chip Package Structures Having Embedded Chip Interconnect Bridges And Fan-out Redistribution Layers
App 20210265275 - Rubin; Joshua M. ; et al. | 2021-08-26 |
Back-side memory element with local memory select transistor
Grant 11,101,318 - Kumar , et al. August 24, 2 | 2021-08-24 |
Multi-chip package structures having embedded chip interconnect bridges and fan-out redistribution layers
Grant 11,094,637 - Rubin , et al. August 17, 2 | 2021-08-17 |
Through-silicon-via fabrication in planar quantum devices
Grant 11,088,310 - Rubin , et al. August 10, 2 | 2021-08-10 |
Micro-fluidic channels having various critical dimensions
Grant 11,081,424 - Bonam , et al. August 3, 2 | 2021-08-03 |
Reducing gate resistance in stacked vertical transport field effect transistors
Grant 11,069,679 - Wu , et al. July 20, 2 | 2021-07-20 |
Semiconductor wafer having trenches with varied dimensions for multi-chip modules
Grant 11,049,844 - Bonam , et al. June 29, 2 | 2021-06-29 |
Multi-chip Package Structure Having High Density Chip Interconnect Bridge With Embedded Power Distribution Network
App 20210183773 - Rubin; Joshua M. ; et al. | 2021-06-17 |
Multi-chip Package Structures Formed By Joining Chips To Pre-positioned Chip Interconnect Bridge Devices
App 20210159211 - Rubin; Joshua M. ; et al. | 2021-05-27 |
Multi-chip Package Structures Having Embedded Chip Interconnect Bridges And Fan-out Redistribution Layers
App 20210134728 - Rubin; Joshua M. ; et al. | 2021-05-06 |
Multi-chip Package Structures Formed With Interconnect Bridge Devices And Chip Packages With Discrete Redistribution Layers
App 20210134724 - Rubin; Joshua M. ; et al. | 2021-05-06 |
Multiple chip bridge connector
Grant 10,991,635 - McHerron , et al. April 27, 2 | 2021-04-27 |
Three-dimensional monolithic vertical transistor memory cell with unified inter-tier cross-couple
Grant 10,971,504 - Rubin April 6, 2 | 2021-04-06 |
Power distribution networks for monolithic three-dimensional semiconductor integrated circuit devices
Grant 10,910,312 - Rubin , et al. February 2, 2 | 2021-02-02 |
Power distribution networks for monolithic three-dimensional semiconductor integrated circuit devices
Grant 10,903,165 - Rubin , et al. January 26, 2 | 2021-01-26 |
Fabrication of a MIM capacitor structure with via etch control with integrated maskless etch tuning layers
Grant 10,903,307 - Rubin , et al. January 26, 2 | 2021-01-26 |
Multiple Chip Bridge Connector
App 20210020529 - McHerron; Dale Curtis ; et al. | 2021-01-21 |
Semiconductor Wafer Having Trenches With Varied Dimensions For Multi-chip Modules
App 20210005573 - Bonam; Ravi K. ; et al. | 2021-01-07 |
Micro-fluidic Channels Having Various Critical Dimensions
App 20200402889 - BONAM; RAVI K. ; et al. | 2020-12-24 |
Forming isolated contacts in a stacked vertical transport field effect transistor (VTFET)
Grant 10,833,081 - Zhang , et al. November 10, 2 | 2020-11-10 |
Reducing Gate Resistance In Stacked Vertical Transport Field Effect Transistors
App 20200343241 - WU; Heng ; et al. | 2020-10-29 |
Through-silicon-via Fabrication In Planar Quantum Devices
App 20200343434 - Rubin; Joshua M. ; et al. | 2020-10-29 |
Forming Isolated Contacts In A Stacked Vertical Transport Field Effect Transistor (vtfet)
App 20200328209 - Zhang; Chen ; et al. | 2020-10-15 |
Vertical field-effect transistors for monolithic three-dimensional semiconductor integrated circuit devices
Grant 10,770,460 - Rubin Sep | 2020-09-08 |
Contact Formation For Stacked Vertical Transport Field-effect Transistors
App 20200273755 - Wu; Heng ; et al. | 2020-08-27 |
Gate metal patterning for tight pitch applications
Grant 10,755,985 - Mochizuki , et al. A | 2020-08-25 |
Interlayer via contacts for monolithic three-dimensional semiconductor integrated circuit devices
Grant 10,748,901 - Rubin , et al. A | 2020-08-18 |
High cutoff frequency metal-insulator-metal capacitors implemented using via contact configurations
Grant 10,714,420 - Rubin , et al. | 2020-07-14 |
Middle of the line subtractive self-aligned contacts
Grant 10,714,393 - Rubin , et al. | 2020-07-14 |
High Cutoff Frequency Metal-insulator-metal Capacitors Implemented Using Via Contact Configurations
App 20200211955 - Rubin; Joshua M. ; et al. | 2020-07-02 |
Vertical field-effect transistors for monolithic three-dimensional semiconductor integrated circuit devices
Grant 10,700,067 - Rubin | 2020-06-30 |
Independent gate FinFET with backside gate contact
Grant 10,700,209 - Hook , et al. | 2020-06-30 |
Vertical transport field-effect transistor architecture
Grant 10,692,768 - Rubin , et al. | 2020-06-23 |
Vertical Field-effect Transistors For Monolithic Three-dimensional Semiconductor Integrated Circuit Devices
App 20200152629 - Rubin; Joshua M. | 2020-05-14 |
Three-dimensional Monolithic Vertical Transistor Memory Cell With Unified Inter-tier Cross-couple
App 20200144274 - Rubin; Joshua M. | 2020-05-07 |
Power Distribution Networks For Monolithic Three-dimensional Semiconductor Integrated Circuit Devices
App 20200135645 - Rubin; Joshua M. ; et al. | 2020-04-30 |
Power Distribution Networks For Monolithic Three-dimensional Semiconductor Integrated Circuit Devices
App 20200135646 - Rubin; Joshua M. ; et al. | 2020-04-30 |
Vertical field-effect transistors for monolithic three-dimensional semiconductor integrated circuit devices
Grant 10,636,791 - Rubin | 2020-04-28 |
Interlayer Via Contacts For Monolithic Three-dimensional Semiconductor Integrated Circuit Devices
App 20200126987 - Rubin; Joshua M. ; et al. | 2020-04-23 |
Vertical Field-effect Transistors For Monolithic Three-dimensional Semiconductor Integrated Circuit Devices
App 20200119011 - Rubin; Joshua M. | 2020-04-16 |
Vertical Field-effect Transistors For Monolithic Three-dimensional Semiconductor Integrated Circuit Devices
App 20200119012 - Rubin; Joshua M. | 2020-04-16 |
Integrated Circuit (ic) Package With Hetrogenous Ic Chip Interposer
App 20200111773 - Kumar; Arvind ; et al. | 2020-04-09 |
Bulk to silicon on insulator device
Grant 10,608,080 - Hook , et al. | 2020-03-31 |
Power distribution networks for monolithic three-dimensional semiconductor integrated circuit devices
Grant 10,607,938 - Rubin , et al. | 2020-03-31 |
Gate metal patterning for tight pitch applications
Grant 10,600,694 - Mochizuki , et al. | 2020-03-24 |
Three-dimensional monolithic vertical transistor memory cell with unified inter-tier cross-couple
Grant 10,593,681 - Rubin | 2020-03-17 |
Three-dimensional Monolithic Vertical Transistor Memory Cell With Unified Inter-tier Cross-couple
App 20200066732 - Rubin; Joshua M. | 2020-02-27 |
Fabrication Of A Mim Capacitor Structure With Via Etch Control With Integrated Maskless Etch Tuning Layers
App 20200066834 - Rubin; Joshua M. ; et al. | 2020-02-27 |
Multilayer buried metal-insultor-metal capacitor structures
Grant 10,546,918 - Reznicek , et al. Ja | 2020-01-28 |
Multilayer Buried Metal-insultor-metal Capacitor Structures
App 20190371883 - REZNICEK; Alexander ; et al. | 2019-12-05 |
Fabrication of a MIM capacitor structure with via etch control with integrated maskless etch tuning layers
Grant 10,483,344 - Rubin , et al. Nov | 2019-11-19 |
Fabrication Of A Mim Capacitor Structure With Via Etch Control With Integrated Maskless Etch Tuning Layers
App 20190333983 - Rubin; Joshua M. ; et al. | 2019-10-31 |
Multilayer buried metal-insultor-metal capacitor structures
Grant 10,461,148 - Reznicek , et al. Oc | 2019-10-29 |
Back-side memory element with local memory select transistor
Grant 10,446,606 - Kumar , et al. Oc | 2019-10-15 |
Back-side Memory Element With Local Memory Select Transistor
App 20190259807 - Kumar; Arvind ; et al. | 2019-08-22 |
Middle of the line subtractive self-aligned contacts
Grant 10,373,874 - Rubin , et al. | 2019-08-06 |
Bulk to silicon on insulator device
Grant 10,332,959 - Hook , et al. | 2019-06-25 |
Self-aligned air gap spacer for nanosheet CMOS devices
Grant 10,243,043 - Mochizuki , et al. | 2019-03-26 |
Mirror contact capacitor
Grant 10,229,915 - Hook , et al. | 2019-03-12 |
Tensile strained high percentage silicon germanium alloy FinFETS
Grant 10,211,341 - Doris , et al. Feb | 2019-02-19 |
Wafer bonding edge protection using double patterning with edge exposure
Grant 10,199,352 - Rubin Fe | 2019-02-05 |
Metallized junction FinFET structures
Grant 10,192,888 - Doris , et al. Ja | 2019-01-29 |
Back-side Memory Element With Local Memory Select Transistor
App 20190027535 - Kumar; Arvind ; et al. | 2019-01-24 |
Self-aligned Air Gap Spacer For Nanosheet Cmos Devices
App 20180358435 - Mochizuki; Shogo ; et al. | 2018-12-13 |
Fully silicided linerless middle-of-line (MOL) contact
Grant 10,147,815 - Rubin , et al. De | 2018-12-04 |
Independent gate FinFET with backside gate contact
Grant 10,128,377 - Hook , et al. November 13, 2 | 2018-11-13 |
Vertical field effect transistor with metallic bottom region
Grant 10,121,877 - Hook , et al. November 6, 2 | 2018-11-06 |
Gate Metal Patterning For Tight Pitch Applications
App 20180308767 - Mochizuki; Shogo ; et al. | 2018-10-25 |
Gate Metal Patterning For Tight Pitch Applications
App 20180308768 - Mochizuki; Shogo ; et al. | 2018-10-25 |
Gate Metal Patterning For Tight Pitch Applications
App 20180308766 - Mochizuki; Shogo ; et al. | 2018-10-25 |
Gate metal patterning for tight pitch applications
Grant 10,103,065 - Mochizuki , et al. October 16, 2 | 2018-10-16 |
Middle Of The Line Subtractive Self-aligned Contacts
App 20180261511 - Rubin; Joshua M. ; et al. | 2018-09-13 |
Independent Gate Finfet With Backside Gate Contact
App 20180248041 - Hook; Terence B. ; et al. | 2018-08-30 |
Independent Gate Finfet With Backside Gate Contact
App 20180248042 - Hook; Terence B. ; et al. | 2018-08-30 |
Middle of the line subtractive self-aligned contacts
Grant 10,032,674 - Rubin , et al. July 24, 2 | 2018-07-24 |
Mirrored contact CMOS with self-aligned source, drain, and back-gate
Grant 9,997,607 - Hook , et al. June 12, 2 | 2018-06-12 |
Bulk to silicon on insulator device
Grant 9,991,339 - Hook , et al. June 5, 2 | 2018-06-05 |
Bulk to silicon on insulator device
Grant 9,978,871 - Hook , et al. May 22, 2 | 2018-05-22 |
Self-aligned air gap spacer for nanosheet CMOS devices
Grant 9,954,058 - Mochizuki , et al. April 24, 2 | 2018-04-24 |
Mirror Contact Capacitor
App 20180102367 - HOOK; Terence B. ; et al. | 2018-04-12 |
Bulk To Silicon On Insulator Device
App 20180083134 - Hook; Terence B. ; et al. | 2018-03-22 |
Tensile Strained High Percentage Silicon Germanium Alloy Finfets
App 20180047847 - Doris; Bruce B. ; et al. | 2018-02-15 |
Mirror contact capacitor
Grant 9,881,925 - Hook , et al. January 30, 2 | 2018-01-30 |
Mirrored Contact Cmos With Self-aligned Source, Drain, And Back-gate
App 20180006126 - Hook; Terence B. ; et al. | 2018-01-04 |
Mirror Contact Capacitor
App 20170373070 - HOOK; Terence B. ; et al. | 2017-12-28 |
Fully silicided linerless middle-of-line (MOL) contact
Grant 9,853,151 - Rubin , et al. December 26, 2 | 2017-12-26 |
Tensile strained high percentage silicon germanium alloy FinFETs
Grant 9,812,571 - Doris , et al. November 7, 2 | 2017-11-07 |
Wafer Bonding Edge Protection Using Double Patterning With Edge Exposure
App 20170317052 - Rubin; Joshua M. | 2017-11-02 |
Bulk To Silicon On Insulator Device
App 20170294533 - Hook; Terence B. ; et al. | 2017-10-12 |
Bulk To Silicon On Insulator Device
App 20170294534 - Hook; Terence B. ; et al. | 2017-10-12 |
Bulk To Silicon On Insulator Device
App 20170294340 - Hook; Terence B. ; et al. | 2017-10-12 |
Bulk To Silicon On Insulator Device
App 20170294507 - Hook; Terence B. ; et al. | 2017-10-12 |
Bulk to silicon on insulator device
Grant 9,786,546 - Hook , et al. October 10, 2 | 2017-10-10 |
Selective oxidation of buried silicon-germanium to form tensile strained silicon FinFETs
Grant 9,761,498 - Doris , et al. September 12, 2 | 2017-09-12 |
Wafer bonding edge protection using double patterning with edge exposure
Grant 9,741,684 - Rubin August 22, 2 | 2017-08-22 |
Defect reduction in channel silicon germanium on patterned silicon
Grant 9,735,062 - Doris , et al. August 15, 2 | 2017-08-15 |
Metallized Junction Finfet Structures
App 20170221926 - Doris; Bruce B. ; et al. | 2017-08-03 |
Interlayer via
Grant 9,711,501 - Basker , et al. July 18, 2 | 2017-07-18 |
Fully Silicided Linerless Middle-of-line (mol) Contact
App 20170194202 - Rubin; Joshua M. ; et al. | 2017-07-06 |
Selective Oxidation Of Buried Silicon-germanium To Form Tensile Strained Silicon Finfets
App 20170170079 - Doris; Bruce B. ; et al. | 2017-06-15 |
Middle Of The Line Subtractive Self-aligned Contacts
App 20170162443 - Rubin; Joshua M. ; et al. | 2017-06-08 |
Middle Of The Line Subtractive Self-aligned Contacts
App 20170162437 - Rubin; Joshua M. ; et al. | 2017-06-08 |
Metallized junction FinFET structures
Grant 9,634,028 - Doris , et al. April 25, 2 | 2017-04-25 |
Fully silicided linerless middle-of-line (MOL) contact
Grant 9,634,113 - Rubin , et al. April 25, 2 | 2017-04-25 |
Metallized junction FinFET structures
Grant 9,627,410 - Doris , et al. April 18, 2 | 2017-04-18 |
Tensile Strained High Percentage Silicon Germanium Alloy Finfets
App 20170092765 - Doris; Bruce B. ; et al. | 2017-03-30 |
Fully Silicided Linerless Middle-of-line (mol) Contact
App 20170084742 - Rubin; Joshua M. ; et al. | 2017-03-23 |
Fully Silicided Linerless Middle-of-line (mol) Contact
App 20170084713 - Rubin; Joshua M. ; et al. | 2017-03-23 |
Wafer Bonding Edge Protection Using Double Patterning With Edge Exposure
App 20170053891 - Rubin; Joshua M. | 2017-02-23 |
Selective oxidation of buried silicon-germanium to form tensile strained silicon FinFETs
Grant 9,570,590 - Doris , et al. February 14, 2 | 2017-02-14 |
Metallized Junction Finfet Structures
App 20160343734 - Doris; Bruce B. ; et al. | 2016-11-24 |
Metallized Junction Finfet Structures
App 20160343572 - Doris; Bruce B. ; et al. | 2016-11-24 |
CMOS structures with selective tensile strained NFET fins and relaxed PFET fins
Grant 9,472,621 - Doris , et al. October 18, 2 | 2016-10-18 |
CMOS structures with selective tensile strained NFET fins and relaxed PFET fins
Grant 9,349,798 - Doris , et al. May 24, 2 | 2016-05-24 |
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