Rozeau; Olivier

Patent Applications and Registrations

Patent applications and USPTO patent grants for Rozeau; Olivier.The latest application filed is for "photosensitive detector with self-aligned 3d junction and gate".

Company Profile

4.10.11

Rozeau; Olivier - Moirans FR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Computer implemented method for determining intrinsic parameter in a stacked nanowires MOSFET Grant 10,914,703 - Rozeau , et al. February 9, 2	2021-02-09
Photosensitive detector with self-aligned 3D junction and gate Grant 10,777,701 - Kadura , et al. Sept	2020-09-15
Front-illuminated photosensitive logic cell Grant 10,290,667 - Rozeau , et al.	2019-05-14
Photosensitive Detector With Self-aligned 3d Junction And Gate App 20190074398 - Kadura; Lina ; et al.	2019-03-07
Computer Implemented Method For Determining Intrinsic Parameter In A Stacked Nanowires Mosfet App 20180156749 - ROZEAU; Olivier ; et al.	2018-06-07
Manufacturing of self aligned interconnection elements for 3D integrated circuits Grant 9,761,583 - Fenouillet-Beranger , et al. September 12, 2	2017-09-12
Front-illuminated Photosensitive Logic Cell App 20170125458 - ROZEAU; Olivier ; et al.	2017-05-04
Manufacturing Of Self Aligned Interconnection Elements For 3d Integrated Circuits App 20160365342 - FENOUILLET-BERANGER; Claire ; et al.	2016-12-15
Computer Implemented Method For Calculating A Charge Density At A Gate Interface Of A Double Gate Transistor App 20160019327 - POIROUX; Thierry ; et al.	2016-01-21
Computer implemented method for calculating a charge density at a gate interface of a double gate transistor Grant 9,235,668 - Poiroux , et al. January 12, 2	2016-01-12
Photonic Cmos Inverter App 20150338720 - GRENOUILLET; Laurent ; et al.	2015-11-26
Air-spacer Mos Transistor App 20150091089 - Niebojewski; Heimanu ; et al.	2015-04-02
Method for making asymmetric double-gate transistors Grant 8,399,316 - Vinet , et al. March 19, 2	2013-03-19
Method for fabricating asymmetric double-gate transistors by which asymmetric and symmetric double-gate transistors can be made on the same substrate Grant 8,324,057 - Vinet , et al. December 4, 2	2012-12-04
Method for making asymmetric double-gate transistors by which asymmetric and symmetric double-gate transistors can be made on the same substrate Grant 8,232,168 - Vinet , et al. July 31, 2	2012-07-31
Method for fabricating asymmetric double-gate transistors by which asymmetric and symmetric double-gate transistors can be made on the same substrate Grant 8,105,906 - Vinet , et al. January 31, 2	2012-01-31
Method For Fabricating Asymmetric Double-gate Transistors By Which Asymmetric And Symmetric Double-gate Transistors Can Be Made On The Same Substrate App 20100320541 - Vinet; Maud ; et al.	2010-12-23
Method For Making Asymmetric Double-gate Transistors By Which Asymmetric And Symmetric Double-gate Transistors Can Be Made On The Same Substrate App 20100317167 - Vinet; Maud ; et al.	2010-12-16
Method For Making Asymmetric Double-gate Transistors App 20100178743 - Vinet; Maud ; et al.	2010-07-15
Method For Fabricating Asymmetric Double-gate Transistors By Which Asymmetric And Symmetric Double-gate Transistors Can Be Made On The Same Substrate App 20100096700 - Vinet; Maud ; et al.	2010-04-22

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