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Virtualized-in-hardware Input Output Memory Management
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Modeless instruction execution with 64/32-bit addressing
Grant 10,671,391 - Sudhakar , et al. | 2020-06-02 |
Processors supporting atomic writes to multiword memory locations and methods
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Hardware virtualized input output memory management unit
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Translation lookaside buffer
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Processors and methods for cache sparing stores
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Translation Lookaside Buffer
App 20180089102 - Rozario; Ranjit J. ; et al. | 2018-03-29 |
Translation lookaside buffer
Grant 9,830,275 - Rozario , et al. November 28, 2 | 2017-11-28 |
Apparatus And Methods For Out Of Order Item Selection And Status Updating
App 20170293646 - Rozario; Ranjit J. ; et al. | 2017-10-12 |
Processors Supporting Atomic Writes To Multiword Memory Locations & Methods
App 20170293486 - Rozario; Ranjit J. ; et al. | 2017-10-12 |
Read Discards In A Processor System With Write-back Caches
App 20170293556 - Rozario; Ranjit J. | 2017-10-12 |
Crossing pipelined data between circuitry in different clock domains
Grant 9,740,454 - Rozario August 22, 2 | 2017-08-22 |
Pipelined ECC-protected memory access
Grant 9,740,557 - Rozario , et al. August 22, 2 | 2017-08-22 |
Processors Supporting Endian Agnostic SIMD Instructions and Methods
App 20170123792 - Rozario; Ranjit J. ; et al. | 2017-05-04 |
Translation Lookaside Buffer
App 20160342523 - Rozario; Ranjit J. ; et al. | 2016-11-24 |
Crossing Pipelined Data Between Circuitry In Different Clock Domains
App 20160253151 - Rozario; Ranjit J. | 2016-09-01 |
Crossing pipelined data between circuitry in different clock domains
Grant 9,367,286 - Rozario June 14, 2 | 2016-06-14 |
Processors And Methods For Cache Sparing Stores
App 20160055083 - Rozario; Ranjit J. ; et al. | 2016-02-25 |
Pipelined Ecc-protected Memory Access
App 20150242274 - Rozario; Ranjit J. ; et al. | 2015-08-27 |
Modeless Instruction Execution With 64/32-bit Addressing
App 20150242212 - Sudhakar; Ranganathan ; et al. | 2015-08-27 |
Crossing Pipelined Data between Circuitry in Different Clock Domains
App 20150067384 - Rozario; Ranjit J. | 2015-03-05 |
Digital counter segmented into short and long access time memory
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Digital Counter Segmented Into Short And Long Access Time Memory
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Scheduler for a direct memory access device having multiple channels
Grant 7,254,651 - Rozario , et al. August 7, 2 | 2007-08-07 |
Free memory manager scheme and cache
Grant 6,961,822 - Rozario , et al. November 1, 2 | 2005-11-01 |
Free memory manager scheme and cache
App 20040078525 - Rozario, Ranjit J. ; et al. | 2004-04-22 |
Free memory manager scheme and cache
Grant 6,618,793 - Rozario , et al. September 9, 2 | 2003-09-09 |
Scheduler for a data memory access having multiple channels
App 20020078267 - Rozario, Ranjit J. ; et al. | 2002-06-20 |
Free memory manager scheme and cache
App 20020078303 - Rozario, Ranjit J. ; et al. | 2002-06-20 |
Arbitrating FIFO implementation which positions input request in a buffer according to its status
Grant 6,253,262 - Rozario , et al. June 26, 2 | 2001-06-26 |
Computer system including system controller with a write buffer and plural read buffers for decoupled busses
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