loadpatents
name:-0.023823022842407
name:-0.048762798309326
name:-0.0013909339904785
Roy; Richard S. Patent Filings

Roy; Richard S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Roy; Richard S..The latest application filed is for "integrated circuit devices and methods".

Company Profile
0.53.18
  • Roy; Richard S. - Dublin CA
  • Roy; Richard S - Dublin CA US
  • Roy; Richard S. - Danville CA
  • Roy; Richard S. - Pleasanton CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Integrated circuit devices and methods
Grant 9,966,130 - Clark , et al. May 8, 2
2018-05-08
Integrated Circuit Devices and Methods
App 20170301395 - Clark; Lawrence T. ;   et al.
2017-10-19
Integrated circuit devices and methods
Grant 9,741,428 - Clark , et al. August 22, 2
2017-08-22
Dram-Type Device With Low Variation Transistor Peripheral Circuits, and Related Methods
App 20160336056 - Clark; Lawrence T. ;   et al.
2016-11-17
Transistor array structure
Grant 9,449,967 - Roy , et al. September 20, 2
2016-09-20
Dynamic random access memory (DRAM) with low variation transistor peripheral circuits
Grant 9,431,068 - Clark , et al. August 30, 2
2016-08-30
Integrated Circuit Devices and Methods
App 20160232964 - Clark; Lawrence T. ;   et al.
2016-08-11
Integrated circuit devices and methods
Grant 9,362,291 - Clark , et al. June 7, 2
2016-06-07
High utilization multi-partitioned serial memory
Grant 9,342,471 - Miller , et al. May 17, 2
2016-05-17
Circuits and methods for measuring circuit elements in an integrated circuit device
Grant 9,297,850 - Clark , et al. March 29, 2
2016-03-29
Porting a circuit design from a first semiconductor process to a second semiconductor process
Grant 9,117,746 - Clark , et al. August 25, 2
2015-08-25
Hierarchical multi-bank multi-port memory organization
Grant 9,030,894 - Roy , et al. May 12, 2
2015-05-12
Multiple VDD clock buffer
Grant 8,994,415 - Roy March 31, 2
2015-03-31
Ring oscillator with NMOS or PMOS variation insensitivity
Grant 8,988,153 - Roy March 24, 2
2015-03-24
Semiconductor chip layout
Grant 8,901,747 - Miller , et al. December 2, 2
2014-12-02
Semiconductor chip layout with staggered Tx and Tx data lines
Grant 8,890,332 - Miller , et al. November 18, 2
2014-11-18
Circuits and methods for measuring circuit elements in an integrated circuit device
Grant 8,837,230 - Clark , et al. September 16, 2
2014-09-16
Integrated circuit devices and methods
Grant 8,811,068 - Clark , et al. August 19, 2
2014-08-19
Porting a circuit design from a first semiconductor process to a second semiconductor process
Grant 8,806,395 - Clark , et al. August 12, 2
2014-08-12
Dram-type Device With Low Variation Transistor Peripheral Circuits, And Related Methods
App 20140119099 - Clark; Lawrence T. ;   et al.
2014-05-01
Separate pass gate controlled sense amplifier
Grant 8,681,574 - Roy , et al. March 25, 2
2014-03-25
Porting a circuit design from a first semiconductor process to a second semiconductor process
Grant 8,645,878 - Clark , et al. February 4, 2
2014-02-04
Hierarchical Multi-Bank Multi-Port Memory Organization
App 20130336074 - Roy; Richard S. ;   et al.
2013-12-19
Circuits and methods for measuring circuit elements in an integrated circuit device
Grant 8,599,623 - Clark , et al. December 3, 2
2013-12-03
Semiconductor Chip Layout With Staggered Tx And Tx Data Liness
App 20130313723 - Miller; Michael J. ;   et al.
2013-11-28
Hierarchical multi-bank multi-port memory organization
Grant 8,547,774 - Roy , et al. October 1, 2
2013-10-01
Hierarchical organization of large memory blocks
Grant 8,539,196 - Roy September 17, 2
2013-09-17
Methods for accessing DRAM cells using separate bit line control
Grant 8,451,675 - Roy , et al. May 28, 2
2013-05-28
Multiple cycle memory write completion
Grant 8,446,755 - Roy May 21, 2
2013-05-21
Integrated circuit package with segregated Tx and Rx data channels
Grant 8,368,217 - Miller , et al. February 5, 2
2013-02-05
Integrated Circuit Package With Segregated Tx And Rx Data Channels
App 20120267769 - Miller; Michael J. ;   et al.
2012-10-25
Separate Pass Gate Controlled Sense Amplifier
App 20120250441 - Roy; Richard S. ;   et al.
2012-10-04
Methods For Accessing DRAM Cells Using Separate Bit Line Control
App 20120250442 - Roy; Richard S. ;   et al.
2012-10-04
Multiple Cycle Memory Write Completion
App 20120140581 - Roy; Richard S.
2012-06-07
Multiple cycle memory write completion
Grant 8,139,399 - Roy March 20, 2
2012-03-20
High Utilization Multi-Partitioned Serial Memory
App 20110191548 - Miller; Michael J. ;   et al.
2011-08-04
Hierarchical Multi-Bank Multi-Port Memory Organization
App 20110188335 - Roy; Richard S. ;   et al.
2011-08-04
Hierarchical Organization Of Large Memory Blocks
App 20110191564 - Roy; Richard S.
2011-08-04
Multiple Cycle Memory Write Completion
App 20110085398 - Roy; Richard S.
2011-04-14
Simultaneous access and cache loading in a hierarchically organized memory circuit
Grant 6,886,078 - Roy April 26, 2
2005-04-26
Distributed interface for parallel testing of multiple devices using a single tester channel
Grant 6,678,850 - Roy , et al. January 13, 2
2004-01-13
Electronic component overlapping dice of unsingulated semiconductor wafer
Grant 6,664,628 - Khandros , et al. December 16, 2
2003-12-16
Distributed interface for parallel testing of multiple devices using a single tester channel
App 20030126534 - Roy, Richard S. ;   et al.
2003-07-03
Efficient parallel testing of semiconductor devices using a known good device to generate expected responses
Grant 6,559,671 - Miller , et al. May 6, 2
2003-05-06
Distributed interface for parallel testing of multiple devices using a single tester channel
Grant 6,499,121 - Roy , et al. December 24, 2
2002-12-24
Efficient parallel testing of semiconductor devices using a known good device to generate expected responses
App 20020175697 - Miller, Charles A. ;   et al.
2002-11-28
Parallel testing of integrated circuit devices using cross-DUT and within-DUT comparisons
Grant 6,480,978 - Roy , et al. November 12, 2
2002-11-12
Compilable block clear mechanism on per I/O basis for high-speed memory
Grant 6,466,504 - Roy October 15, 2
2002-10-15
Efficient parallel testing of integrated circuit devices using a known good device to generate expected responses
Grant 6,452,411 - Miller , et al. September 17, 2
2002-09-17
Electronic component overlapping dice of unsingulated semiconductor wafer
App 20020074653 - Khandros, Igor Y. ;   et al.
2002-06-20
Fast read/write cycle memory device having a self-timed read/write control circuit
Grant 6,392,957 - Shubat , et al. May 21, 2
2002-05-21
Interconnect assemblies and methods including ancillary electronic component connected in immediate proximity of semiconductor device
Grant 6,330,164 - Khandros , et al. December 11, 2
2001-12-11
Self-timed clock circuitry in a multi-bank memory instance using a common timing synchronization node
Grant 6,282,131 - Roy August 28, 2
2001-08-28
Method and apparatus for optimizing high speed performance and hot carrier lifetime in a MOS integrated circuit
Grant 5,426,375 - Roy , et al. June 20, 1
1995-06-20
Input protection circuit for CMOS devices
Grant 5,159,518 - Roy October 27, 1
1992-10-27
Static ram with high speed, low power reset
Grant 4,928,266 - Abbott , et al. May 22, 1
1990-05-22
Static ram with write recovery in selected portion of memory array
Grant 4,926,384 - Roy May 15, 1
1990-05-15
Static ram with common data line equalization
Grant 4,878,198 - Roy October 31, 1
1989-10-31

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