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Substantially L-shaped silicide for contact
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Structure and method for manufacturing asymmetric devices
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Structure and Method for Manufacturing Asymmetric Devices
App 20120217585 - Nayfeh; Hasan M. ; et al. | 2012-08-30 |
Structure and method for manufacturing asymmetric devices
Grant 8,232,151 - Nayfeh , et al. July 31, 2 | 2012-07-31 |
Structure And Method For Manufacturing Asymmetric Devices
App 20110254059 - Nayfeh; Hasan M. ; et al. | 2011-10-20 |
Structure and method for manufacturing asymmetric devices
Grant 8,034,692 - Nayfeh , et al. October 11, 2 | 2011-10-11 |
Method of creating asymmetric field-effect-transistors
Grant 8,017,483 - Freeman , et al. September 13, 2 | 2011-09-13 |
Structure and method to form multilayer embedded stressors
Grant 7,960,798 - Luo , et al. June 14, 2 | 2011-06-14 |
Structure And Method For Manufacturing Asymmetric Devices
App 20110089499 - Nayfeh; Hasan M. ; et al. | 2011-04-21 |
Method Of Creating Asymmetric Field-effect-transistors
App 20100330763 - Freeman; Gregory G. ; et al. | 2010-12-30 |
Dual stress memory technique method and related structure
Grant 7,785,950 - Fang , et al. August 31, 2 | 2010-08-31 |
Structure And Method To Form Multilayer Embedded Stressors
App 20100059764 - Luo; Zhijiong ; et al. | 2010-03-11 |
Structure and method to form multilayer embedded stressors
Grant 7,618,866 - Luo , et al. November 17, 2 | 2009-11-17 |
Spacer Undercut Filler, Method Of Manufacture Thereof And Articles Comprising The Same
App 20090057755 - Dyer; Thomas W. ; et al. | 2009-03-05 |
N-channel MOSFETs comprising dual stressors, and methods for forming the same
Grant 7,473,608 - Li , et al. January 6, 2 | 2009-01-06 |
Substantially L-shaped Silicide For Contact And Related Method
App 20080283934 - Luo; Zhijiong ; et al. | 2008-11-20 |
Method of forming substantially L-shaped silicide contact for a semiconductor device
Grant 7,442,619 - Luo , et al. October 28, 2 | 2008-10-28 |
Method to engineer etch profiles in Si substrate for advanced semiconductor devices
Grant 7,442,618 - Chong , et al. October 28, 2 | 2008-10-28 |
Structure And Method To Form Multilayer Embedded Stressors
App 20080006818 - Luo; Zhijiong ; et al. | 2008-01-10 |
Semiconductor Structure Including Isolation Region With Variable Linewidth And Method For Fabrication Therof
App 20070293016 - Luo; Zhijiong ; et al. | 2007-12-20 |
N-channel Mosfets Comprising Dual Stressors, And Methods For Forming The Same
App 20070281413 - Li; Jinghong H. ; et al. | 2007-12-06 |
Substantially L-shaped Silicide For Contact And Related Method
App 20070267753 - Luo; Zhijiong ; et al. | 2007-11-22 |
N-channel MOSFETs comprising dual stressors, and methods for forming the same
Grant 7,279,758 - Li , et al. October 9, 2 | 2007-10-09 |
Semiconductor devices and methods of manufacture thereof
App 20070134861 - Han; Jin-Ping ; et al. | 2007-06-14 |
Dual Stress Memory Technique Method And Related Structure
App 20070105299 - Fang; Sunfei ; et al. | 2007-05-10 |
Method to engineer etch profiles in Si substrate for advanced semiconductor devices
App 20070020861 - Chong; Yung Fu ; et al. | 2007-01-25 |
Salicide formation method
Grant 6,916,729 - Fang , et al. July 12, 2 | 2005-07-12 |
Salicide formation method
App 20040203229 - Fang, Sunfei ; et al. | 2004-10-14 |
Method for low topography semiconductor device formation
Grant 6,797,569 - Colavito , et al. September 28, 2 | 2004-09-28 |
Method for low topography semiconductor device formation
Grant 6,624,486 - Colavito , et al. September 23, 2 | 2003-09-23 |
Method For Low Topography Semiconductor Device Formation
App 20030170941 - Colavito, David B. ; et al. | 2003-09-11 |
Method for forming junction on insulator (JOI) structure
Grant 6,544,874 - Mandelman , et al. April 8, 2 | 2003-04-08 |
Method For Forming Junction On Insulator (joi) Structure
App 20030032272 - Mandelman, Jack A. ; et al. | 2003-02-13 |
Semiconductor Device With Junction Isolation
App 20020179905 - Colavito, David ; et al. | 2002-12-05 |
Method for low topography semiconductor device formation
App 20020175369 - Colavito, David B. ; et al. | 2002-11-28 |
Patterned buried insulator
App 20020072206 - Chen, Bomy A. ; et al. | 2002-06-13 |
Self-aligned junction isolation
Grant 6,403,482 - Rovedo , et al. June 11, 2 | 2002-06-11 |
Buried strap for DRAM using junction isolation technique
Grant 6,391,703 - Rovedo , et al. May 21, 2 | 2002-05-21 |
Junction isolation
Grant 6,352,903 - Rovedo , et al. March 5, 2 | 2002-03-05 |
Apparatus and method for detecting defective NVRAM cells
Grant 6,256,755 - Hook , et al. July 3, 2 | 2001-07-03 |
Process for making and programming a flash memory array
Grant 5,681,770 - Ogura , et al. October 28, 1 | 1997-10-28 |
Process for making and programming a flash memory array
Grant 5,672,892 - Ogura , et al. September 30, 1 | 1997-09-30 |
Process for making and programming a flash memory array
Grant 5,654,917 - Ogura , et al. August 5, 1 | 1997-08-05 |
Packing density for flash memories by using a pad oxide
Grant 5,643,813 - Acocella , et al. July 1, 1 | 1997-07-01 |
Packing density for flash memories
Grant 5,622,881 - Acocella , et al. April 22, 1 | 1997-04-22 |
Process for making and programming a flash memory array
Grant 5,541,130 - Ogura , et al. July 30, 1 | 1996-07-30 |
Method of forming thin silicon mesas having uniform thickness
Grant 5,334,281 - Doerre , et al. August 2, 1 | 1994-08-02 |
Thin SOI layer for fully depleted field effect transistors
Grant 5,264,395 - Bindal , et al. November 23, 1 | 1993-11-23 |
Field effect-transistor with asymmetrical structure
Grant H986 - Codella , et al. November 5, 1 | 1991-11-05 |
Vertical bipolar transistor with collector and base extensions
Grant 4,982,257 - Akbar , et al. January 1, 1 | 1991-01-01 |
Vertical bipolar transistor
Grant 4,957,875 - Akbar , et al. September 18, 1 | 1990-09-18 |
Method for manufacturing a Bi-CMOS device
Grant 4,868,135 - Ogura , et al. September 19, 1 | 1989-09-19 |
Sidewall spacers for CMOS circuit stress relief/isolation and method for making
Grant 4,729,006 - Dally , et al. March 1, 1 | 1988-03-01 |
Method for removing protuberances at the surface of a semiconductor wafer using a chem-mech polishing technique
Grant 4,671,851 - Beyer , et al. June 9, 1 | 1987-06-09 |
Method of preventing asymmetric etching of lines in sub-micrometer range sidewall images transfer
Grant 4,648,937 - Ogura , et al. March 10, 1 | 1987-03-10 |
Self-aligned lateral bipolar transistors
Grant 4,641,170 - Ogura , et al. February 3, 1 | 1987-02-03 |
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