| Patent | Date |
|---|
Bonded substrate for an integrated circuit containing a planar intrinsic gettering zone
Grant 7,052,973 - Linn , et al. May 30, 2 | 2006-05-30 |
Bonded wafer with metal silicidation
Grant 6,909,146 - Linn , et al. June 21, 2 | 2005-06-21 |
Bonded substrate for an integrated circuit containing a planar intrinsic gettering zone
Grant 6,825,532 - Linn , et al. November 30, 2 | 2004-11-30 |
BICMOS process with low temperature coefficient resistor (TCRL)
Grant 6,812,108 - Hemmenway , et al. November 2, 2 | 2004-11-02 |
BiCMOS process with low temperature coefficient resistor (TCRL)
Grant 6,798,024 - Hemmenway , et al. September 28, 2 | 2004-09-28 |
Bonded substrate for an integrated circuit containing a planar intrinsic gettering zone
App 20040180512 - Linn, Jack H. ; et al. | 2004-09-16 |
BiCMOS process with low temperature coefficient resistor (TCRL)
App 20030157778 - Hemmenway, Donald ; et al. | 2003-08-21 |
Sc-2 Based Pre-thermal Treatment Wafer Cleaning Process
App 20020189640 - LINN, JACK H. ; et al. | 2002-12-19 |
Power trench transistor device source region formation using silicon spacer
App 20010022379 - Brush, Linda S. ; et al. | 2001-09-20 |
Method for forming a bonded substrate containing a planar intrinsic gettering zone and substrate formed by said method
App 20010016399 - Linn, Jack H. ; et al. | 2001-08-23 |
Method for forming a bonded substrate containing a planar intrinsic gettering zone and substrate formed by said method
Grant 6,255,195 - Linn , et al. July 3, 2 | 2001-07-03 |
Power trench transistor device source region formation using silicon spacer
Grant 6,246,090 - Brush , et al. June 12, 2 | 2001-06-12 |
SC-2 based pre-thermal treatment wafer cleaning process
Grant 5,932,022 - Linn , et al. August 3, 1 | 1999-08-03 |
Bonded wafer processing with oxidative bonding
Grant 5,849,627 - Linn , et al. December 15, 1 | 1998-12-15 |
Bonded wafer
Grant 5,744,852 - Linn , et al. April 28, 1 | 1998-04-28 |
Bonded wafer and method of fabrication thereof
Grant 5,603,779 - Linn , et al. February 18, 1 | 1997-02-18 |
Bonded wafer processing with metal silicidation
Grant 5,569,620 - Linn , et al. October 29, 1 | 1996-10-29 |
Bonded wafer processing
Grant 5,517,047 - Linn , et al. May 14, 1 | 1996-05-14 |
Bonded wafer processing with metal silicidation
Grant 5,387,555 - Linn , et al. February 7, 1 | 1995-02-07 |
Bonded wafer processing
Grant 5,362,667 - Linn , et al. November 8, 1 | 1994-11-08 |
Wafer bonding using trapped oxidizing vapor
Grant 5,334,273 - Short , et al. August 2, 1 | 1994-08-02 |
Wafer bonding process employing liquid oxidant
Grant 5,266,135 - Short , et al. November 30, 1 | 1993-11-30 |
Method of fabricating SOI wafer with SiGe as an etchback film in a BESOI process
Grant 5,240,876 - Gaul , et al. August 31, 1 | 1993-08-31 |
SOI wafer with sige
Grant 5,218,213 - Gaul , et al. June 8, 1 | 1993-06-08 |
Ultra-thin circuit fabrication by controlled wafer debonding
Grant 5,091,331 - Delgado , et al. February 25, 1 | 1992-02-25 |
Manufacturing ultra-thin dielectrically isolated wafers
Grant 5,081,061 - Rouse , et al. January 14, 1 | 1992-01-14 |
Manufacturing ultra-thin wafer using a handle wafer
Grant 5,034,343 - Rouse , et al. July 23, 1 | 1991-07-23 |
Method of fabricating back diffused bonded oxide substrates
Grant 4,968,628 - Delgado , et al. November 6, 1 | 1990-11-06 |
Dielectric isolation process using double wafer bonding
Grant 4,851,078 - Short , et al. July 25, 1 | 1989-07-25 |
Precision Polishing Of Semiconductor Crystal Wafers
Grant 3,699,722 - Davidson , et al. October 24, 1 | 1972-10-24 |
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