| Patent | Date |
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Apparatus and method to electrostatically remove foreign matter from substrate surfaces
Grant 11,376,640 - Rotondaro , et al. July 5, 2 | 2022-07-05 |
System and Method for Wet Chemical Etching in Semiconductor Processing
App 20210384049 - Bassett; Derek William ; et al. | 2021-12-09 |
System and Methods for Wafer Drying
App 20210287919 - Hurd; Trace ; et al. | 2021-09-16 |
Apparatus and Method to Electrostatically Remove Foreign Matter from Substrate Surfaces
App 20200101500 - Rotondaro; Antonio Luis Pacheco ; et al. | 2020-04-02 |
Method of treating a microelectronic substrate using dilute TMAH
Grant 10,256,163 - Printz , et al. | 2019-04-09 |
Method and apparatus for dynamic control of the temperature of a wet etch process
Grant 10,096,480 - Rotondaro , et al. October 9, 2 | 2018-10-09 |
Method Of Treating A Microelectronic Substrate Using Dilute Tmah
App 20170141005 - Printz; Wallace P. ; et al. | 2017-05-18 |
Method And Apparatus For Dynamic Control Of The Temperature Of A Wet Etch Process
App 20170092550 - Rotondaro; Antonio Luis Pacheco ; et al. | 2017-03-30 |
Method And Apparatus For Drying Semiconductor Substrates Using Liquid Carbon Dioxide
App 20170092484 - Brown; Ian J. ; et al. | 2017-03-30 |
Defect prevention on SRAM cells that incorporate selective epitaxial regions
Grant 8,384,138 - Rotondaro February 26, 2 | 2013-02-26 |
Semiconductor Device With Gate-undercutting Recessed Region
App 20110318901 - ROTONDARO; Antonio Luis Pacheco ; et al. | 2011-12-29 |
Semiconductor device having a dislocation loop located within a boundary created by source/drain regions and a method of manufacture therefor
Grant 7,691,714 - Rotondaro , et al. April 6, 2 | 2010-04-06 |
Defect control in gate dielectrics
Grant 7,601,578 - Colombo , et al. October 13, 2 | 2009-10-13 |
Work function control of metals
Grant 7,601,577 - Chambers , et al. October 13, 2 | 2009-10-13 |
Crystallographic preferential etch to define a recessed-region for epitaxial growth
Grant 7,528,072 - Rotondaro , et al. May 5, 2 | 2009-05-05 |
Methods to selectively protect NMOS regions, PMOS regions, and gate layers during EPI process
Grant 7,514,309 - Sridhar , et al. April 7, 2 | 2009-04-07 |
N-type Semiconductor Component With Improved Dopant Implantation Profile And Method Of Forming Same
App 20080268628 - Kohli; Puneet ; et al. | 2008-10-30 |
Work Function Control Of Metals
App 20080044957 - Chambers; James Joseph ; et al. | 2008-02-21 |
Method to prevent defects on SRAM cells that incorporate selective epitaxial regions
App 20070290192 - Rotondaro; Antonio Luis Pacheco | 2007-12-20 |
Semiconductor Device Having Multiple Work Functions and Method of Manufacture Therefor
App 20070284676 - Alshareef; Husam N. ; et al. | 2007-12-13 |
Crystallographic Preferential Etch To Define A Recessed-region For Epitaxial Growth
App 20070249168 - Rotondaro; Antonio Luis Pacheco ; et al. | 2007-10-25 |
Semiconductor device having multiple work functions and method of manufacture therefor
Grant 7,226,826 - Alshareef , et al. June 5, 2 | 2007-06-05 |
Method to reduce transistor gate to source/drain overlap capacitance by incorporation of carbon
Grant 7,199,011 - Mansoori , et al. April 3, 2 | 2007-04-03 |
Work function control of metals
App 20070054446 - Chambers; James Joseph ; et al. | 2007-03-08 |
Method to selectively strain NMOS devices using a cap poly layer
Grant 7,172,936 - Sridhar , et al. February 6, 2 | 2007-02-06 |
Methods to selectively protect NMOS regions, PMOS regions, and gate layers during EPI process
App 20070020839 - Sridhar; Seetharaman ; et al. | 2007-01-25 |
System and method for extraction of C-V characteristics of ultra-thin oxides
Grant 7,088,123 - Yang , et al. August 8, 2 | 2006-08-08 |
Semiconductor device having a dislocation loop located within a boundary created by source/drain regions and a method of manufacture therefor
App 20060163651 - Rotondaro; Antonio Luis Pacheco ; et al. | 2006-07-27 |
Control of high-k gate dielectric film composition profile for property optimization
Grant 7,071,519 - Colombo , et al. July 4, 2 | 2006-07-04 |
Use of indium to define work function of p-type doped polysilicon
Grant 7,026,218 - Rotondaro , et al. April 11, 2 | 2006-04-11 |
Semiconductor device having multiple work functions and method of manufacture therefor
App 20050233533 - Alshareef, Husam N. ; et al. | 2005-10-20 |
Method to reduce transistor gate to source/drain overlap capacitance by incorporaton of carbon
App 20050014353 - Mansoori, Majid Movahed ; et al. | 2005-01-20 |
Use of indium to define work function of p-type doped polysilicon
App 20040222443 - Rotondaro, Antonio Luis Pacheco ; et al. | 2004-11-11 |
Use of indium to define work function of p-type doped polysilicon
Grant 6,803,611 - Rotondaro , et al. October 12, 2 | 2004-10-12 |
Methods for fabricating transistor gate structures
Grant 6,787,425 - Rotondaro , et al. September 7, 2 | 2004-09-07 |
Control of high -k gate dielectric film composition profile for property optimization
App 20040129969 - Colombo, Luigi ; et al. | 2004-07-08 |
Use of indium to define work function of p-type doped polysilicon of polysilicon germanium
App 20040129988 - Rotondaro, Antonio Luis Pacheco ; et al. | 2004-07-08 |
High-K gate dielectric defect gettering using dopants
App 20040127000 - Colombo, Luigi ; et al. | 2004-07-01 |
Methods for sputter deposition of high-k dielectric films
Grant 6,750,126 - Visokay , et al. June 15, 2 | 2004-06-15 |
Bilayer deposition to avoid unwanted interfacial reactions during high K gate dielectric processing
Grant 6,696,332 - Visokay , et al. February 24, 2 | 2004-02-24 |
Method for the selective removal of high-k dielectrics
Grant 6,656,852 - Rotondaro , et al. December 2, 2 | 2003-12-02 |
Bilayer deposition to avoid unwanted interfacial reactions during high K gate dielectric processing
App 20030116804 - Visokay, Mark Robert ; et al. | 2003-06-26 |
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