Rothwell; Mary E.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Rothwell; Mary E..The latest application filed is for "lithography for fabricating josephson junctions".

Company Profile

3.19.21

Rothwell; Mary E. - Ridgefield CT
Rothwell; Mary E. - Yorktown Heights NY
Rothwell; Mary E. - Armonk NY US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Lithography For Fabricating Josephson Junctions App 20220037578 - Rodbell; Kenneth P. ; et al.	2022-02-03
Enhanced adhesive materials and processes for 3D applications Grant 11,168,234 - Hedrick , et al. November 9, 2	2021-11-09
Enhanced adhesive materials and processes for 3D applications Grant 10,767,084 - Hedrick , et al. Sep	2020-09-08
Enhanced Adhesive Materials And Processes For 3d Applications App 20200165494 - Hedrick; James L. ; et al.	2020-05-28
Enhanced Adhesive Materials And Processes For 3d Applications App 20190378781 - Hedrick; James L. ; et al.	2019-12-12
Enhanced Adhesive Materials And Processes For 3d Applications App 20180340100 - Hedrick; James L. ; et al.	2018-11-29
Suspended superconducting qubits Grant 10,008,655 - Chang , et al. June 26, 2	2018-06-26
Enhanced adhesive materials and processes for 3D applications Grant 9,994,741 - Hedrick , et al. June 12, 2	2018-06-12
Suspended superconducting qubits Grant 9,716,219 - Chang , et al. July 25, 2	2017-07-25
Enhanced Adhesive Materials And Processes For 3d Applications App 20170166784 - Hedrick; James L. ; et al.	2017-06-15
Removal of spurious microwave modes via flip-chip crossover Grant 9,531,055 - Abraham , et al. December 27, 2	2016-12-27
Chip mode isolation and cross-talk reduction through buried metal layers and through-vias Grant 9,520,547 - Abraham , et al. December 13, 2	2016-12-13
Method of fabricating a coplanar waveguide device including removal of spurious microwave modes via flip-chip crossover Grant 9,455,392 - Abraham , et al. September 27, 2	2016-09-27
Chip mode isolation and cross-talk reduction through buried metal layers and through-vias Grant 9,397,283 - Abraham , et al. July 19, 2	2016-07-19
Removal Of Spurious Microwave Modes Via Flip-chip Crossover App 20160204331 - Abraham; David W. ; et al.	2016-07-14
Removal Of Spurious Microwave Modes Via Flip-chip Crossover App 20160204330 - Abraham; David W. ; et al.	2016-07-14
Removal of spurious microwave modes via flip-chip crossover Grant 9,219,298 - Abraham , et al. December 22, 2	2015-12-22
Suspended Superconducting Qubits App 20150340584 - Chang; Josephine B. ; et al.	2015-11-26
Suspended superconducting qubits Grant 9,177,814 - Chang , et al. November 3, 2	2015-11-03
Suspended Superconducting Qubits App 20150311422 - Chang; Josephine B. ; et al.	2015-10-29
Lock and key through-via method for wafer level 3D integration and structures produced thereby Grant 9,064,717 - Purushothaman , et al. June 23, 2	2015-06-23
Chip Mode Isolation And Cross-talk Reduction Through Buried Metal Layers And Through-vias App 20150155468 - Abraham; David W. ; et al.	2015-06-04
Low-loss superconducting devices Grant 8,954,125 - Corcoles Gonzalez , et al. February 10, 2	2015-02-10
Chip Mode Isolation And Cross-talk Reduction Through Buried Metal Layers And Through-vias App 20140274725 - Abraham; David W. ; et al.	2014-09-18
Removal Of Spurious Microwave Modes Via Flip-chip Crossover App 20140264287 - Abraham; David W. ; et al.	2014-09-18
Suspended Superconducting Qubits App 20140264286 - Chang; Josephine B. ; et al.	2014-09-18
Low-loss Superconducting Devices App 20130029848 - Gonzalez; Antonio D. Corcoles ; et al.	2013-01-31
Lock and key through-via method for wafer level 3D integration and structures produced Grant 8,093,099 - Purushothaman , et al. January 10, 2	2012-01-10
Lock and Key Through-Via Method for Wafer Level 3D Integration and Structures Produced Thereby App 20110111560 - Purushothaman; Sampath ; et al.	2011-05-12
Lock and key through-via method for wafer level 3 D integration and structures produced Grant 7,855,455 - Purushothaman , et al. December 21, 2	2010-12-21
Lock and Key Through-Via Method for Wafer Level 3D Integration and Structures Produced App 20100200992 - Purushothaman; Sampath ; et al.	2010-08-12
Lock and Key Through-Via Method for Wafer Level 3 D Integration and Structures Produced App 20100078770 - Purushothaman; Sampath ; et al.	2010-04-01

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