loadpatents
name:-0.0045440196990967
name:-0.02408504486084
name:-0.00096797943115234
Roth; Scott S. Patent Filings

Roth; Scott S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Roth; Scott S..The latest application filed is for "semiconductor structure with sacrificial anode and method for forming".

Company Profile
0.22.5
  • Roth; Scott S. - Austin TX
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Semiconductor structure with sacrificial anode and method for forming
Grant 10,199,339 - Chopin , et al. Fe
2019-02-05
Semiconductor Structure With Sacrificial Anode and Method for Forming
App 20160329288 - CHOPIN; SHEILA F. ;   et al.
2016-11-10
Semiconductor Structure With Sacrificial Anode And Method For Forming
App 20140346663 - Chopin; Sheila F. ;   et al.
2014-11-27
Monitor circuit for determining the lifetime of a semiconductor device
Grant 8,824,114 - Perkey , et al. September 2, 2
2014-09-02
Monitor Circuit For Determining The Lifetime Of A Semiconductor Device
App 20110261491 - PERKEY; JASON C. ;   et al.
2011-10-27
Method of stimulating die circuitry and structure therefor
Grant 7,741,195 - Rashid , et al. June 22, 2
2010-06-22
Method Of Stimulating Die Circuitry And Structure Therefor
App 20070275539 - Rashid; Mohammed K. ;   et al.
2007-11-29
Contact structure and method of formation
Grant 6,285,073 - Cooper , et al. September 4, 2
2001-09-04
Electrically programmable read-only memory cell
Grant 5,616,941 - Roth , et al. April 1, 1
1997-04-01
Method of making a contact structure
Grant 5,604,159 - Cooper , et al. February 18, 1
1997-02-18
Vertically formed neuron transister having a floating gate and a control gate
Grant 5,583,360 - Roth , et al. December 10, 1
1996-12-10
Process for forming an electrically programmable read-only memory cell
Grant 5,543,339 - Roth , et al. August 6, 1
1996-08-06
Method of making a vertically formed neuron transistor having a floating gate and a control gate and a method of formation
Grant 5,480,820 - Roth , et al. January 2, 1
1996-01-02
Encapsulation method for localized oxidation of silicon with trench isolation
Grant 5,455,194 - Vasquez , et al. October 3, 1
1995-10-03
Semiconductor device and method of formation
Grant 5,445,107 - Roth , et al. August 29, 1
1995-08-29
Self-aligned thin film transistor
Grant 5,308,997 - Cooper , et al. May 3, 1
1994-05-03
Method for forming a via structure and semiconductor device having the same
Grant 5,286,674 - Roth , et al. February 15, 1
1994-02-15
Method for planarizing a layer of material
Grant 5,272,117 - Roth , et al. December 21, 1
1993-12-21
Method for forming pitch independent contacts and a semiconductor device having the same
Grant 5,219,793 - Cooper , et al. June 15, 1
1993-06-15
ITLDD transistor having a variable work function
Grant 5,210,435 - Roth , et al. May 11, 1
1993-05-11
Method for forming a buried contact
Grant 5,126,285 - Kosa , et al. June 30, 1
1992-06-30
Process for the formation of elevated source and drain structures in a semiconductor device
Grant 5,118,639 - Roth , et al. June 2, 1
1992-06-02
ITLDD transistor having variable work function and method for fabricating the same
Grant 5,061,647 - Roth , et al. October 29, 1
1991-10-29
Encapsulation method for localized oxidation of silicon
Grant 4,927,780 - Roth , et al. May 22, 1
1990-05-22
Method for prevention of autodoping of epitaxial layers
Grant 4,662,956 - Roth , et al. May 5, 1
1987-05-05

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