Rossi; Nace

Patent Applications and Registrations

Patent applications and USPTO patent grants for Rossi; Nace.The latest application filed is for "thermally stable bicmos fabrication method and bipolar junction trnasistors formed according to the method".

Company Profile

0.18.22

Rossi; Nace - Singapore SG

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor device and a method of manufacture therefor Grant 8,872,311 - Rossi , et al. October 28, 2	2014-10-28
Integrated circuit system with contact distribution film Grant 8,685,861 - Yong , et al. April 1, 2	2014-04-01
Method for forming a bipolar junction transistor and a metal oxide semiconductor field effect transistor Grant 8,084,313 - Nanda , et al. December 27, 2	2011-12-27
Robust shallow trench isolation structures and a method for forming shallow trench isolation structures Grant 8,022,481 - Nanda , et al. September 20, 2	2011-09-20
Method to improve metal defects in semiconductor device fabrication Grant 7,982,286 - Rossi , et al. July 19, 2	2011-07-19
Shallow trench isolation structures and a method for forming shallow trench isolation structures Grant 7,906,407 - Rossi , et al. March 15, 2	2011-03-15
Thermally Stable Bicmos Fabrication Method And Bipolar Junction Trnasistors Formed According To The Method App 20100273301 - Nanda; Arun K. ; et al.	2010-10-28
Semiconductor device and a method of manufacture therefor Grant 7,811,944 - Rossi , et al. October 12, 2	2010-10-12
Thermally stable BiCMOS fabrication method and bipolar junction transistors formed according to the method Grant 7,776,678 - Nanda , et al. August 17, 2	2010-08-17
Device and method to eliminate shorting induced by via to metal misalignment Grant 7,675,179 - Singh , et al. March 9, 2	2010-03-09
Methods And Systems For Controlling Accumulation Of Electrical Charge During Semiconductor Etching Processes App 20090139962 - Wang; Edward Aiguo ; et al.	2009-06-04
Robust Shallow Trench Isolation Structures And A Method For Forming Shallow Trench Isolation Structures App 20090127651 - Nanda; Arun K. ; et al.	2009-05-21
A Semiconductor Device And Method Of Manufacture Therefor App 20090108359 - Rossi; Nace ; et al.	2009-04-30
Robust shallow trench isolation structures and a method for forming shallow trench isolation structures Grant 7,514,336 - Nanda , et al. April 7, 2	2009-04-07
THERMALLY STABLE BiCMOS FABRICATION METHOD AND BIPOLAR JUNCTION TRANSISTOR FORMED ACCORDING TO THE METHOD App 20090011553 - Nanda; Arun K. ; et al.	2009-01-08
Thermally stable BiCMOS fabrication method and bipolar junction transistors formed according to the method Grant 7,439,119 - Nanda , et al. October 21, 2	2008-10-21
Semiconductor device and a method of manufacture therefor App 20080079083 - Rossi; Nace ; et al.	2008-04-03
Shallow Trench Isolation Structures and a Method for Forming Shallow Trench Isolation Structures App 20080057672 - Rossi; Nace ; et al.	2008-03-06
Integrated Circuit System With Contact Film App 20080029853 - Yong; Chih Ping ; et al.	2008-02-07
Method To Improve Metal Defects In Semiconductor Device Fabrication App 20080014728 - Rossi; Nace ; et al.	2008-01-17
Junction field effect transistor and method for manufacture App 20070278539 - Dyson; Mark Victor ; et al.	2007-12-06
Trench isolation structure and method of manufacture therefor Grant 7,279,393 - Nanda , et al. October 9, 2	2007-10-09
Thermally stable BiCMOS fabrication method and bipolar junction transistors formed according to the method App 20070202642 - Nanda; Arun K. ; et al.	2007-08-30
Device And Method To Eliminate Shorting Induced By Via To Metal Misalignment App 20070190803 - Singh; Ranbir ; et al.	2007-08-16
Control of wafer warpage during backend processing Grant 7,247,556 - Nanda , et al. July 24, 2	2007-07-24
Robust shallow trench isolation structures and a method for forming shallow trench isolation structures App 20070152294 - Nanda; Arun K. ; et al.	2007-07-05
Device and method to eliminate shorting induced by via to metal misalignment Grant 7,235,489 - Singh , et al. June 26, 2	2007-06-26
Shallow trench isolation structures and a method for forming shallow trench isolation structures App 20070066074 - Rossi; Nace ; et al.	2007-03-22
Shallow Trench Isolation Structures Comprising A Graded Doped Sacrificial Silicon Dioxide Material And A Method For Forming Shallow Trench Isolation Structures App 20060286739 - Rossi; Nace ; et al.	2006-12-21
Shallow trench isolation structures comprising a graded doped sacrificial silicon dioxide material and a method for forming shallow trench isolation structures Grant 7,141,486 - Rossi , et al. November 28, 2	2006-11-28
Control of wafer warpage during backend processing App 20060194428 - Nanda; Arun K. ; et al.	2006-08-31
Trench isolation structure and method of manufacture therefor App 20060068562 - Nanda; Arun ; et al.	2006-03-30
Semiconductor device and a method of manufacture therefor Grant 7,005,724 - Rossi , et al. February 28, 2	2006-02-28
Semiconductor device and a method of manufacture therefor App 20050282372 - Rossi, Nace ; et al.	2005-12-22
Interconnect structure including tungsten nitride and a method of manufacture therefor App 20050269709 - Merchant, Sailesh ; et al.	2005-12-08
Device and method to eliminate shorting induced by via to metal misalignment App 20050260843 - Singh, Ranbir ; et al.	2005-11-24
Semiconductor device and a method of manufacture therefor App 20050179115 - Rossi, Nace ; et al.	2005-08-18
Semiconductor device and a method of manufacture therefor App 20050179116 - Rossi, Nace ; et al.	2005-08-18

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.