Ronchetti; Bruce Joseph

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ronchetti; Bruce Joseph.The latest application filed is for "reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices".

Company Profile

1.23.18

Ronchetti; Bruce Joseph - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices Grant 10,983,800 - Eisen , et al. April 20, 2	2021-04-20
Processing of multiple instruction streams in a parallel slice processor Grant 10,157,064 - Eisen , et al. Dec	2018-12-18
Reconfigurable Processor With Load-store Slices Supporting Reorder And Controlling Access To Cache Slices App 20180285118 - Eisen; Lee Evan ; et al.	2018-10-04
Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices Grant 10,083,039 - Eisen , et al. September 25, 2	2018-09-25
Reconfigurable Processor With Load-store Slices Supporting Reorder And Controlling Access To Cache Slices App 20180150300 - Eisen; Lee Evan ; et al.	2018-05-31
Reconfigurable parallel execution and load-store slice processor Grant 9,977,678 - Eisen , et al. May 22, 2	2018-05-22
Reconfigurable processing method with modes controlling the partitioning of clusters and cache slices Grant 9,971,602 - Eisen , et al. May 15, 2	2018-05-15
Parallel slice processor with dynamic instruction stream mapping Grant 9,690,585 - Eisen , et al. June 27, 2	2017-06-27
Processing of multiple instruction streams in a parallel slice processor Grant 9,690,586 - Eisen , et al. June 27, 2	2017-06-27
Processing Of Multiple Instruction Streams In A Parallel Slice Processor App 20170168837 - Eisen; Lee Evan ; et al.	2017-06-15
Processing of multiple instruction streams in a parallel slice processor Grant 9,672,043 - Eisen , et al. June 6, 2	2017-06-06
Parallel slice processor with dynamic instruction stream mapping Grant 9,665,372 - Eisen , et al. May 30, 2	2017-05-30
Reconfigurable Parallel Execution And Load-store Slice Processing Methods App 20160202991 - Eisen; Lee Evan ; et al.	2016-07-14
Reconfigurable Parallel Execution And Load-store Slice Processor App 20160202989 - Eisen; Lee Evan ; et al.	2016-07-14
Parallel Slice Processor With Dynamic Instruction Stream Mapping App 20150324204 - Eisen; Lee Evan ; et al.	2015-11-12
Processing Of Multiple Instruction Streams In A Parallel Slice Processor App 20150324205 - Eisen; Lee Evan ; et al.	2015-11-12
Processing Of Multiple Instruction Streams In A Parallel Slice Processor App 20150324207 - Eisen; Lee Evan ; et al.	2015-11-12
Parallel Slice Processor With Dynamic Instruction Stream Mapping App 20150324206 - Eisen; Lee Evan ; et al.	2015-11-12
Managing instructions for more efficient load/store unit usage Grant 8,271,765 - Bose , et al. September 18, 2	2012-09-18
Adaptive data prefetch Grant 8,156,287 - Bose , et al. April 10, 2	2012-04-10
Managing Instructions For More Efficient Load/store Unit Usage App 20100262808 - Bose; Pradip ; et al.	2010-10-14
Adaptive Data Prefetch System and Method App 20100180081 - Bose; Pradip ; et al.	2010-07-15
Auxiliary mechanism to manage instruction restart and restart coming in a lookahead processor Grant 7,752,354 - Dooley , et al. July 6, 2	2010-07-06
Method to optimize effective page number to real page number translation path from page table entries match resumption of execution stream Grant 7,660,965 - Hinojosa , et al. February 9, 2	2010-02-09
Mechanism in a Multi-Threaded Microprocessor to Maintain Best Case Demand Instruction Redispatch App 20080209177 - Frommer; Scott Bruce ; et al.	2008-08-28
Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch Grant 7,380,062 - Frommer , et al. May 27, 2	2008-05-27
Method To Optimize Effective Page Number To Real Page Number Translation Path From Page Table Entries Match Resumption Of Execution Stream App 20080104599 - Hinojosa; Joaquin ; et al.	2008-05-01
Method to optimize effective page number to real page number translation path from page table entries match resumption of execution stream Grant 7,350,051 - Hinojosa , et al. March 25, 2	2008-03-25
Method, apparatus, and computer program product for sharing data in a cache among threads in an SMT processor Grant 7,318,127 - Hrusecky , et al. January 8, 2	2008-01-08
Mechanism and apparatus allowing an N-way set associative cache, implementing a hybrid pseudo-LRU replacement algorithm, to have N L1 miss fetch requests simultaneously inflight regardless of their congruence class Grant 7,284,094 - Hrusecky , et al. October 16, 2	2007-10-16
Auxiliary mechanism to manage instruction restart and restart coming in a lookahead processor App 20060184822 - Dooley; Miles Robert ; et al.	2006-08-17
Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch App 20060184739 - Frommer; Scott Bruce ; et al.	2006-08-17
Method, apparatus, and computer program product for sharing data in a cache among threads in an SMT processor App 20060184741 - Hrusecky; David Allen ; et al.	2006-08-17
Mechanism and apparatus allowing an N-way set associative cache, implementing a hybrid pseudo-LRU replacement algorithm, to have N L1 miss fetch requests simultaneously inflight regardless of their congruence class App 20060179227 - Hrusecky; David Allen ; et al.	2006-08-10
Method to optimize effective page number to real page number translation path from page table entries match resumption of execution stream App 20060179264 - Hinojosa; Joaquin ; et al.	2006-08-10
Apparatus and method of utilizing Alias Hit signals to detect errors within the real address tag arrays Grant 6,640,293 - Paredes , et al. October 28, 2	2003-10-28
Method and system for speculatively processing a load instruction before completion of a preceding synchronization instruction Grant 6,484,230 - Konigsburg , et al. November 19, 2	2002-11-19
System and method for merging multiple outstanding load miss instructions Grant 6,336,168 - Frederick, Jr. , et al. January 1, 2	2002-01-01
System and method for permitting out-of-order execution of load and store instructions Grant 6,301,654 - Ronchetti , et al. October 9, 2	2001-10-09
System and method for permitting out-of-order execution of load instructions Grant 6,266,768 - Frederick, Jr. , et al. July 24, 2	2001-07-24
Queuing method and apparatus for facilitating the rejection of sequential instructions in a processor Grant 6,237,081 - Le , et al. May 22, 2	2001-05-22

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