Rombach; Gerd
Patent Applications and Registrations
Patent applications and USPTO patent grants for Rombach; Gerd.The latest application filed is for "continuous coarse-tuned phase locked loop".
- Rombach; Gerd - Munich DE
- Rombach; Gerd - Freising DE
| Patent | Date |
|---|---|
| Continuous coarse-tuned phase locked loop Grant 10,056,911 - Rombach August 21, 2 | 2018-08-21 |
| Continuous Coarse-tuned Phase Locked Loop App 20170179964 - ROMBACH; Gerd | 2017-06-22 |
| High speed, rail-to-rail CMOS differential input stage Grant 9,356,570 - Rombach May 31, 2 | 2016-05-31 |
| High Speed, Rail-to-rail Cmos Differential Input Stage App 20150333705 - Rombach; Gerd | 2015-11-19 |
| Data pipeline with large tuning range of clock signals Grant 8,166,286 - Frank , et al. April 24, 2 | 2012-04-24 |
| Register with process, supply voltage and temperature variation independent propagation delay path Grant 8,111,092 - Rombach , et al. February 7, 2 | 2012-02-07 |
| Phase-locked loop (PLL) circuit and method Grant 7,868,670 - Becke , et al. January 11, 2 | 2011-01-11 |
| Digital data buffer with phase aligner Grant 7,800,975 - Rombach , et al. September 21, 2 | 2010-09-21 |
| Phase-locked loop circuit Grant 7,663,417 - Rombach February 16, 2 | 2010-02-16 |
| Data Pipeline With Large Tuning Range Of Clock Signals App 20080313485 - Frank; Ingolf ; et al. | 2008-12-18 |
| Register With Process, Supply Voltage And Temperature Variation Independent Propagation Delay Path App 20080301485 - Rombach; Gerd ; et al. | 2008-12-04 |
| Digital Data Buffer App 20080215805 - Rombach; Gerd ; et al. | 2008-09-04 |
| Complementary Output Flip Flop App 20080192551 - Rombach; Gerd | 2008-08-14 |
| Phase-locked Loop Circuit App 20080169850 - Rombach; Gerd | 2008-07-17 |
| Phase-locked Loop (pll) Circuit And Method App 20080054960 - Becke; Georg ; et al. | 2008-03-06 |
| Integrated Cmos Circuit With Differential Open Drain Output Driver App 20080042694 - Rombach; Gerd | 2008-02-21 |
| Oscillator App 20070052483 - Dietl; Markus ; et al. | 2007-03-08 |
| PLL circuit having reduced capacitor size Grant 7,154,345 - Moyal , et al. December 26, 2 | 2006-12-26 |
| Digital spread spectrum clock signal generation App 20060159157 - Seibold; Hermann ; et al. | 2006-07-20 |
| Compact PLL circuit App 20050122174 - Moyal, Miki ; et al. | 2005-06-09 |
| A Clock Generator Circuit With A Pll Having An Output Frequency Cycled In A Range To Reduce Unwanted Radiation App 20030062956 - Rombach, Gerd ; et al. | 2003-04-03 |
| CMOS bus driver circuit App 20020024101 - Rombach, Gerd | 2002-02-28 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.
| 