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name:-0.0039670467376709
name:-0.00040912628173828
Roessler; Thomas Patent Filings

Roessler; Thomas

Patent Applications and Registrations

Patent applications and USPTO patent grants for Roessler; Thomas.The latest application filed is for "absorbent article with waist containment member and method of manufacturing thereof".

Company Profile
0.4.7
  • Roessler; Thomas - Appleton WI
  • Roessler; Thomas - Hitzhofen DE
  • Roessler; Thomas - Radebeul DE
  • Roessler; Thomas - Munchen DE
  • Roessler; Thomas - Munich DE
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Absorbent Article With Waist Containment Member And Method Of Manufacturing Thereof
App 20210346212 - Bishop; David F. ;   et al.
2021-11-11
Absorbent article with waist containment member and method of manufacturing thereof
Grant 11,096,836 - Bishop , et al. August 24, 2
2021-08-24
Absorbent Article With Waist Containment Member And Method Of Manufacturing Thereof
App 20180071155 - Bishop; David F. ;   et al.
2018-03-15
Device And Method For Actuating And Diagnosing Stepper Motors
App 20120139454 - Roessler; Thomas ;   et al.
2012-06-07
Advanced automatic deposition profile targeting and control by applying advanced polish endpoint system feedback
Grant 7,899,570 - Ortleb , et al. March 1, 2
2011-03-01
Method for classifying errors in the layout of a semiconductor circuit
Grant 7,716,613 - Meyer , et al. May 11, 2
2010-05-11
Advanced Automatic Deposition Profile Targeting And Control By Applying Advanced Polish Endpoint System Feedback
App 20090036029 - Ortleb; Thomas ;   et al.
2009-02-05
Method For Analyzing The Design Of An Integrated Circuit
App 20080147373 - Roessler; Thomas ;   et al.
2008-06-19
Method For Checking The Layout Of An Integrated Circuit
App 20080148200 - Von Mueffling; Christian ;   et al.
2008-06-19
Method for classifying errors in the layout of a semiconductor circuit
App 20070157142 - Meyer; Dirk ;   et al.
2007-07-05
Method for classifying errors in the layout of a semiconductor circuit
Grant 7,207,016 - Meyer , et al. April 17, 2
2007-04-17

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