Rodgers; Richard S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Rodgers; Richard S..The latest application filed is for "computer system and method for performing a routing supply and demand analysis during the floor planning stage of an integrated circuit design process".

Company Profile

0.11.11

Rodgers; Richard S. - Fort Collins CO US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Computer system and method for performing a routing supply and demand analysis during the floor planning stage of an integrated circuit design process Grant 8,671,376 - Gentry , et al. March 11, 2	2014-03-11
Computer System And Method For Performing A Routing Supply And Demand Analysis During The Floor Planning Stage Of An Integrated Circuit Design Process App 20130263073 - Gentry; Jason T. ; et al.	2013-10-03
System and method for ensuring partitioned block physical compatibility between revisions of an integrated circuit design Grant 8,434,052 - Koenig , et al. April 30, 2	2013-04-30
Determining the placement of semiconductor components on an integrated circuit Grant 7,915,742 - Porter , et al. March 29, 2	2011-03-29
Apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC) Grant 7,580,806 - Rodgers , et al. August 25, 2	2009-08-25
Alpha-particle-tolerant semiconductor die systems, devices, components and methods for optimizing clock rates and minimizing die size Grant 7,451,418 - Porter , et al. November 11, 2	2008-11-11
Determining The Placement Of Semiconductor Components On An Integrated Circuit App 20080230900 - Porter; Howard L. ; et al.	2008-09-25
Determining the placement of semiconductor components on an integrated circuit Grant 7,386,824 - Porter , et al. June 10, 2	2008-06-10
Determining the placement of semiconductor components on an integrated circuit App 20070050599 - Porter; Howard L. ; et al.	2007-03-01
Alpha-particle-tolerant semiconductor die systems, devices, components and methods for optimizing clock rates and minimizing die size App 20070032065 - Porter; Howard L. ; et al.	2007-02-08
Apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC) Grant 7,079,973 - Rodgers , et al. July 18, 2	2006-07-18
Method and apparatus for automating post-tape release VLSI modifications App 20060075370 - Williams; Brett H. ; et al.	2006-04-06
Integrated circuit routing resource optimization algorithm for random port ordering Grant 7,010,641 - Esch, Jr. , et al. March 7, 2	2006-03-07
Method and apparatus for automating VLSI modifications made after routing has been performed App 20060030965 - Williams; Brett H. ; et al.	2006-02-09
Integrated circuit routing resource optimization algorithm for random port ordering App 20050262464 - Esch, Gerald L. JR. ; et al.	2005-11-24
Apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC) App 20050222795 - Rodgers, Richard S. ; et al.	2005-10-06
Integrated circuit routing resource optimization algorithm for random port ordering App 20040177209 - Esch, Gerald L. JR. ; et al.	2004-09-09
Method and apparatus for minimizing clock skew in a balanced tree when interfacing to an unbalanced load Grant 6,769,104 - Rodgers , et al. July 27, 2	2004-07-27
Method and apparatus for minimizing clock skew in a balanced tree when interfacing to an unblalanced load App 20030212971 - Rodgers, Richard S. ; et al.	2003-11-13

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