Robust Chip Inc.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Robust Chip Inc..The latest application filed is for "layout method for soft-error hard electronics, and radiation hardened logic cell".
- Robust Chip Inc. - Pleasanton CA US
| Patent | Date |
|---|---|
| Soft error resilient circuit design method and logic cells Grant 9,083,341 - Lilja July 14, 2 | 2015-07-14 |
| Layout Method For Soft-error Hard Electronics, And Radiation Hardened Logic Cell App 20140019921 - Lilja; Klas Olof | 2014-01-16 |
| Soft Error Hard Electronics Layout Arrangement and Logic Cells App 20130162293 - Lilja; Klas Olof | 2013-06-27 |
| NCAGE Code | 348F7 | ROBUST CHIP INC. |
| CAGE Code | 348F7 | ROBUST CHIP INC. |
| S.A.M. Registration | 348F7 [170882539] | ROBUST CHIP INC. |
| S.A.M. Registration | 348F7 [170882539] | ROBUST CHIP INC. |
| DUNS | 170882539 | ROBUST CHIP INC. |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.
| 