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Robles; Juan Andres Torres Patent Filings

Robles; Juan Andres Torres

Patent Applications and Registrations

Patent applications and USPTO patent grants for Robles; Juan Andres Torres.The latest application filed is for "integrated circuit layout design methodology with process variation bands".

Company Profile
0.18.19
  • Robles; Juan Andres Torres - Wilsonville OR US
  • Robles; Juan Andres Torres - US
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Integrated Circuit Layout Design Methodology With Process Variation Bands
App 20180260512 - Robles; Juan Andres Torres
2018-09-13
Integrated circuit layout design methodology with process variation bands
Grant 9,977,856 - Robles May 22, 2
2018-05-22
Directed Self-Assembly-Aware Layout Decomposition For Multiple Patterning
App 20170220729 - Pikus; Fedor ;   et al.
2017-08-03
Directed self-assembly-aware layout decomposition for multiple patterning
Grant 9,652,581 - Pikus , et al. May 16, 2
2017-05-16
Integrated Circuit Layout Design Methodology With Process Variation Bands
App 20170004250 - Robles; Juan Andres Torres
2017-01-05
Directed Self-Assembly-Aware Layout Decomposition For Multiple Patterning
App 20160292345 - Pikus; Fedor ;   et al.
2016-10-06
Integrated circuit layout design methodology with process variation bands
Grant 9,361,424 - Robles June 7, 2
2016-06-07
Generating guiding patterns for directed self-assembly
Grant 9,330,228 - Robles , et al. May 3, 2
2016-05-03
Grouping layout features for directed self assembly
Grant 9,111,067 - Robles August 18, 2
2015-08-18
Generating Guiding Patterns For Directed Self-Assembly
App 20150227676 - Robles; Juan Andres Torres ;   et al.
2015-08-13
Grouping Layout Features For Directed Self Assembly
App 20150143313 - Robles; Juan Andres Torres
2015-05-21
Generating Guiding Patterns For Directed Self-Assembly
App 20150143323 - Robles; Juan Andres Torres ;   et al.
2015-05-21
Generating guiding patterns for directed self-assembly
Grant 9,032,357 - Robles , et al. May 12, 2
2015-05-12
Integrated Circuit Layout Design Methodology With Process Variation Bands
App 20150067618 - Robles; Juan Andres Torres
2015-03-05
Analysis optimizer
Grant 8,832,609 - Robles , et al. September 9, 2
2014-09-09
Integrated circuit layout design methodology with process variation bands
Grant 8,799,830 - Robles August 5, 2
2014-08-05
Analysis Optimizer
App 20130305195 - Robles; Juan Andres Torres ;   et al.
2013-11-14
Hybrid hotspot detection
Grant 8,504,949 - Robles , et al. August 6, 2
2013-08-06
Hotspot detection based on machine learning
Grant 8,402,397 - Robles , et al. March 19, 2
2013-03-19
Hotspot Detection Based On Machine Learning
App 20130031522 - Robles; Juan Andres Torres ;   et al.
2013-01-31
Hybrid Hotspot Detection
App 20130031518 - Robles; Juan Andres Torres ;   et al.
2013-01-31
Pre-bias optical proximity correction
Grant 8,185,847 - Robles , et al. May 22, 2
2012-05-22
Contrast-based resolution enhancement for photolithographic processing
Grant 8,108,806 - Robles , et al. January 31, 2
2012-01-31
Analysis optimizer
Grant 8,056,022 - Robles , et al. November 8, 2
2011-11-08
Chromeless phase mask layout generation
Grant 7,172,838 - Maurer , et al. February 6, 2
2007-02-06
Defect location identification for microdevice manufacturing and test
App 20060069958 - Sawicki; Joseph D. ;   et al.
2006-03-30
Contrast based resolution enhancing technology
Grant 7,013,439 - Robles , et al. March 14, 2
2006-03-14
Integrated circuit layout design methodology with process variation bands
App 20050251771 - Robles, Juan Andres Torres
2005-11-10
Contrast based resolution enhancement for photolithographic processing
App 20050044513 - Robles, Juan Andres Torres ;   et al.
2005-02-24
Chromeless phase mask layout generation
App 20040063000 - Maurer, Wilhelm ;   et al.
2004-04-01
Contrast based resolution enhancing technology
App 20040005089 - Robles, Juan Andres Torres ;   et al.
2004-01-08

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