Robison; Robert
Patent Applications and Registrations
Patent applications and USPTO patent grants for Robison; Robert.The latest application filed is for "top via on subtractively etched conductive line".
Company Profile
11.37.48
- Robison; Robert - Rexford NY
- Robison; Robert - Colchester VT
- Robison; Robert - Essex Junction VT
Patent Activity
| Patent | Date |
|---|---|
| Single-mask alternating line deposition Grant 11,437,317 - Anderson , et al. September 6, 2 | 2022-09-06 |
| Barrier removal for conductor in top via integration scheme Grant 11,430,735 - Anderson , et al. August 30, 2 | 2022-08-30 |
| Top Via On Subtractively Etched Conductive Line App 20220223473 - Anderson; Brent ; et al. | 2022-07-14 |
| Topological qubit device Grant 11,380,836 - Holmes , et al. July 5, 2 | 2022-07-05 |
| High Aspect Ratio Vias For Integrated Circuits App 20220199521 - Lanzillo; Nicholas Anthony ; et al. | 2022-06-23 |
| Conductive Lines With Subtractive Cuts App 20220181255 - Anderson; Brent ; et al. | 2022-06-09 |
| Interconnects Having Spacers For Improved Top Via Critical Dimension And Overlay Tolerance App 20220157652 - Anderson; Brent A. ; et al. | 2022-05-19 |
| Magnetoresistive random-access memory device including magnetic tunnel junctions Grant 11,335,850 - Yogendra , et al. May 17, 2 | 2022-05-17 |
| Stepped Top Via For Via Resistance Reduction App 20220130718 - Anderson; Brent Alan ; et al. | 2022-04-28 |
| Subtractive line with damascene second line type Grant 11,302,575 - Anderson , et al. April 12, 2 | 2022-04-12 |
| Fully Aligned Top Vias App 20220108922 - Lanzillo; Nicholas Anthony ; et al. | 2022-04-07 |
| Interconnects having spacers for improved top via critical dimension and overlay tolerance Grant 11,295,978 - Anderson , et al. April 5, 2 | 2022-04-05 |
| Top vias with selectively retained etch stops Grant 11,289,371 - Anderson , et al. March 29, 2 | 2022-03-29 |
| Conductive lines with subtractive cuts Grant 11,276,639 - Anderson , et al. March 15, 2 | 2022-03-15 |
| Subtractive Line with Damascene Second Line Type App 20220037205 - Anderson; Brent ; et al. | 2022-02-03 |
| Top Via Stack App 20220028783 - Anderson; Brent Alan ; et al. | 2022-01-27 |
| Top Via Interconnect Having A Line With A Reduced Bottom Dimension App 20220028785 - Anderson; Brent ; et al. | 2022-01-27 |
| Stepped top via for via resistance reduction Grant 11,232,977 - Anderson , et al. January 25, 2 | 2022-01-25 |
| Top Via With Damascene Line And Via App 20220005732 - Clevenger; Lawrence A. ; et al. | 2022-01-06 |
| Etch Stop Layer Removal For Capacitance Reduction In Damascene Top Via Integration App 20220005731 - Penny; Christopher J. ; et al. | 2022-01-06 |
| Top Via With Next Level Line Selective Growth App 20220005761 - Anderson; Brent ; et al. | 2022-01-06 |
| Fully aligned top vias Grant 11,217,481 - Lanzillo , et al. January 4, 2 | 2022-01-04 |
| Well-controlled Edge-to-edge Spacing Between Adjacent Interconnects App 20210384123 - Anderson; Brent ; et al. | 2021-12-09 |
| Top via stack Grant 11,195,792 - Anderson , et al. December 7, 2 | 2021-12-07 |
| Well-controlled edge-to-edge spacing between adjacent interconnects Grant 11,195,795 - Anderson , et al. December 7, 2 | 2021-12-07 |
| Top via interconnect having a line with a reduced bottom dimension Grant 11,189,568 - Anderson , et al. November 30, 2 | 2021-11-30 |
| Etch stop layer removal for capacitance reduction in damascene top via integration Grant 11,177,166 - Penny , et al. November 16, 2 | 2021-11-16 |
| Double patterned lithography using spacer assisted cuts for patterning steps Grant 11,177,160 - Philip , et al. November 16, 2 | 2021-11-16 |
| Top via with next level line selective growth Grant 11,171,084 - Anderson , et al. November 9, 2 | 2021-11-09 |
| Barrier-less Prefilled Via Formation App 20210343589 - Lanzillo; Nicholas Anthony ; et al. | 2021-11-04 |
| Top Via Interconnect Having A Line With A Reduced Bottom Dimension App 20210343643 - Anderson; Brent ; et al. | 2021-11-04 |
| Interconnects Having Spacers For Improved Top Via Critical Dimension And Overlay Tolerance App 20210343585 - Anderson; Brent ; et al. | 2021-11-04 |
| Top via with damascene line and via Grant 11,164,777 - Clevenger , et al. November 2, 2 | 2021-11-02 |
| Patterning line cuts before line patterning using sacrificial fill material Grant 11,158,536 - Dechene , et al. October 26, 2 | 2021-10-26 |
| Top vias with subtractive line formation Grant 11,158,537 - Anderson , et al. October 26, 2 | 2021-10-26 |
| Etch Stop Layer Removal For Capacitance Reduction In Damascene Top Via Integration App 20210327751 - Penny; Christopher J. ; et al. | 2021-10-21 |
| Barrier-less prefilled via formation Grant 11,152,257 - Lanzillo , et al. October 19, 2 | 2021-10-19 |
| Hybrid selective dielectric deposition for aligned via integration Grant 11,152,299 - Lanzillo , et al. October 19, 2 | 2021-10-19 |
| Self-aligned isolation for nanosheet transistor Grant 11,152,464 - Pranatharthi Haran , et al. October 19, 2 | 2021-10-19 |
| Top Via With Next Level Line Selective Growth App 20210313265 - Anderson; Brent ; et al. | 2021-10-07 |
| Top via with hybrid metallization Grant 11,139,201 - Motoyama , et al. October 5, 2 | 2021-10-05 |
| Double Patterned Lithography Using Spacer Assisted Cuts For Patterning Steps App 20210305089 - Philip; Timothy Mathew ; et al. | 2021-09-30 |
| Self-aligned Isolation For Nanosheet Transistor App 20210305361 - Pranatharthi Haran; Balasubramanian S. ; et al. | 2021-09-30 |
| Top Via On Subtractively Etched Conductive Line App 20210296171 - Anderson; Brent ; et al. | 2021-09-23 |
| Magnetoresistive Random-access Memory Device Including Magnetic Tunnel Junctions App 20210288242 - Yogendra; Karthik ; et al. | 2021-09-16 |
| Topological Qubit Device App 20210288238 - Holmes; Steven J. ; et al. | 2021-09-16 |
| Hybrid Selective Dielectric Deposition For Aligned Via Integration App 20210280510 - Lanzillo; Nicholas Anthony ; et al. | 2021-09-09 |
| Self-aligned Block Via Patterning For Dual Damascene Double Patterned Metal Lines App 20210280457 - Philip; Timothy Mathew ; et al. | 2021-09-09 |
| Line Cut Patterning Using Sacrificial Material App 20210265201 - Philip; Timothy Mathew ; et al. | 2021-08-26 |
| Stepped Top Via For Via Resistance Reduction App 20210249302 - Anderson; Brent Alan ; et al. | 2021-08-12 |
| Single-mask Alternating Line Deposition App 20210249351 - Anderson; Brent Alan ; et al. | 2021-08-12 |
| Top Vias With Selectively Retained Etch Stops App 20210233807 - Anderson; Brent ; et al. | 2021-07-29 |
| Top Vias With Subtractive Line Formation App 20210233808 - Anderson; Brent ; et al. | 2021-07-29 |
| Conductive Lines With Subtractive Cuts App 20210225761 - Anderson; Brent ; et al. | 2021-07-22 |
| Barrier-less Prefilled Via Formation App 20210225700 - Lanzillo; Nicholas Anthony ; et al. | 2021-07-22 |
| Top Via With Damascene Line And Via App 20210217661 - Clevenger; Lawrence A. ; et al. | 2021-07-15 |
| Top Via Stack App 20210217696 - Anderson; Brent Alan ; et al. | 2021-07-15 |
| Top via interconnects with wrap around liner Grant 11,062,943 - Motoyama , et al. July 13, 2 | 2021-07-13 |
| Patterning Line Cuts Before Line Patterning Using Sacrificial Fill Material App 20210210379 - Dechene; Daniel James ; et al. | 2021-07-08 |
| Fully Aligned Top Vias App 20210143062 - Lanzillo; Nicholas Anthony ; et al. | 2021-05-13 |
| Top Via With Hybrid Metallization App 20210134664 - Motoyama; Koichi ; et al. | 2021-05-06 |
| Spacer-assisted lithographic double patterning Grant 10,998,193 - Philip , et al. May 4, 2 | 2021-05-04 |
| Spacer-confined epitaxial growth Grant 10,978,573 - Yogendra , et al. April 13, 2 | 2021-04-13 |
| Top Via Interconnects With Wrap Around Liner App 20210043507 - Motoyama; Koichi ; et al. | 2021-02-11 |
| Spacer-confined Epitaxial Growth App 20210013321 - Yogendra; Karthik ; et al. | 2021-01-14 |
| Source and drain contact cut last process to enable wrap-around-contact Grant 10,840,345 - Greene , et al. November 17, 2 | 2020-11-17 |
| Fin isolation to mitigate local layout effects Grant 10,685,866 - Zhou , et al. | 2020-06-16 |
| Source And Drain Contact Cut Last Process To Enable Wrap-around-contact App 20200152756 - GREENE; Andrew ; et al. | 2020-05-14 |
| Source And Drain Contact Cut Last Process To Enable Wrap-around-contact App 20200152751 - Greene; Andrew ; et al. | 2020-05-14 |
| Fin Isolation To Mitigate Local Layout Effects App 20200083088 - Zhou; Huimei ; et al. | 2020-03-12 |
| Structures, methods and applications for electrical pulse anneal processes Grant 8,686,508 - Abou-Khalil , et al. April 1, 2 | 2014-04-01 |
| Structure and method for manufacturing asymmetric devices Grant 8,482,075 - Nayfeh , et al. July 9, 2 | 2013-07-09 |
| Band gap modulated optical sensor Grant 8,008,696 - Cheng , et al. August 30, 2 | 2011-08-30 |
| Methods for forming back-end-of-line resistive semiconductor structures Grant 7,977,201 - Abadeer , et al. July 12, 2 | 2011-07-12 |
| Back-end-of-line Resistive Semiconductor Structures App 20110161896 - Abadeer; Wagdi W. ; et al. | 2011-06-30 |
| Back-end-of-line resistive semiconductor structures Grant 7,939,911 - Abadeer , et al. May 10, 2 | 2011-05-10 |
| Band gap modulated optical sensor Grant 7,888,266 - Cheng , et al. February 15, 2 | 2011-02-15 |
| Field effect transistor and method of fabricating same Grant 7,855,110 - Ontalus , et al. December 21, 2 | 2010-12-21 |
| Back-End-of-Line Resistive Semiconductor Structures App 20100038754 - Abadeer; Wagdi W. ; et al. | 2010-02-18 |
| Methods For Forming Back-End-Of-Line Resistive Semiconductor Structures App 20100041202 - Abadeer; Wagdi W. ; et al. | 2010-02-18 |
| Field Effect Transistor And Method Of Fabricating Same App 20100006952 - Ontalus; Viorel ; et al. | 2010-01-14 |
| Band Gap Modulated Optical Sensor App 20090321786 - Cheng; Kangguo ; et al. | 2009-12-31 |
| Band Gap Modulated Optical Sensor App 20090325337 - Cheng; Kangguo ; et al. | 2009-12-31 |
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