loadpatents
name:-0.0062918663024902
name:-0.016926765441895
name:-0.00086188316345215
Rizzolo; Richard F. Patent Filings

Rizzolo; Richard F.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Rizzolo; Richard F..The latest application filed is for "adaptive power capping in a chip".

Company Profile
0.14.5
  • Rizzolo; Richard F. - Red Hook NY
  • Rizzolo; Richard F. - Poughkeepsie NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Adaptive power capping in a chip
Grant 10,048,734 - Lefurgy , et al. August 14, 2
2018-08-14
Adaptive Power Capping In A Chip
App 20180081413 - Lefurgy; Charles R. ;   et al.
2018-03-22
Adaptive power capping in a chip
Grant 9,874,917 - Lefurgy , et al. January 23, 2
2018-01-23
Temperature-aware microprocessor voltage management
Grant 9,733,685 - Lefurgy , et al. August 15, 2
2017-08-15
Adaptive Power Capping In A Chip
App 20170192477 - Lefurgy; Charles R. ;   et al.
2017-07-06
Temperature-aware Microprocessor Voltage Management
App 20170168534 - Lefurgy; Charles R. ;   et al.
2017-06-15
Voltage droop reduction in a processor
Grant 9,575,529 - Curran , et al. February 21, 2
2017-02-21
Voltage Droop Reduction In A Processor
App 20160098070 - CURRAN; Brian W. ;   et al.
2016-04-07
Method and system for determining repeatable yield detractors of integrated circuits
Grant 6,971,054 - Kurtulik , et al. November 29, 2
2005-11-29
Method and system for determining repeatable yield detractors of integrated circuits
Grant 6,751,765 - Rizzolo , et al. June 15, 2
2004-06-15
Global transition scan based AC method
Grant 6,662,324 - Motika , et al. December 9, 2
2003-12-09
Method to improve a testability analysis of a hierarchical design
Grant 6,532,571 - Gabrielson , et al. March 11, 2
2003-03-11
Scan structure for improving transition fault coverage and scan diagnostics
Grant 6,490,702 - Song , et al. December 3, 2
2002-12-03
Method and apparatus for improving transition fault testability of semiconductor chips
Grant 6,453,436 - Rizzolo , et al. September 17, 2
2002-09-17
Method and system for determining repeatable yield detractors of integrated circuits
App 20020125907 - Kurtulik, Raymond J. ;   et al.
2002-09-12
Technique to decrease the exposure time of infrared imaging of semiconductor chips for failure analysis
Grant 6,442,720 - Koprowski , et al. August 27, 2
2002-08-27
Programmable clock tuning system and method
Grant 5,455,931 - Camporese , et al. October 3, 1
1995-10-03
Encoding for simultaneous switching output noise reduction
Grant 5,142,167 - Temple , et al. August 25, 1
1992-08-25
Two-level differential cascode current switch masterslice
Grant 4,760,289 - Eichelberger , et al. July 26, 1
1988-07-26

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