RIZVI; Saiyid Mohammad Irshad

Patent Applications and Registrations

Patent applications and USPTO patent grants for RIZVI; Saiyid Mohammad Irshad.The latest application filed is for "glitch filter having a switched capacitance and reset stages".

Company Profile

2.14.13

RIZVI; Saiyid Mohammad Irshad - New Delhi IN
Rizvi; Saiyid Mohammad Irshad - New Delhi India IN
Rizvi; Saiyid Mohammad Irshad - Greater Noida N/A IN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Glitch Filter Having A Switched Capacitance And Reset Stages App 20210336606 - TIWARI; Manoj Kumar ; et al.	2021-10-28
Hybrid driver having low output pad capacitance Grant 11,075,624 - Rizvi , et al. July 27, 2	2021-07-27
Hybrid Driver Having Low Output Pad Capacitance App 20200412357 - RIZVI; Saiyid Mohammad Irshad ; et al.	2020-12-31
High performance I2C transmitter and bus supply independent receiver, supporting large supply voltage variations Grant 10,848,147 - Rizvi , et al. November 24, 2	2020-11-24
Biasing cascode transistors of an output buffer circuit for operation over a wide range of supply voltages Grant 10,454,466 - Tiwari , et al. Oc	2019-10-22
Biasing Cascode Transistors Of An Output Buffer Circuit For Operation Over A Wide Range Of Supply Voltages App 20190312575 - TIWARI; Manoj Kumar Kumar ; et al.	2019-10-10
High Performance I2c Transmitter And Bus Supply Independent Receiver, Supporting Large Supply Voltage Variations App 20190158085 - RIZVI; Saiyid Mohammad Irshad ; et al.	2019-05-23
Biasing cascode transistor of an output buffer circuit for operation over a wide range of supply voltages Grant 10,224,922 - Tiwari , et al.	2019-03-05
Apparatus for reference voltage generation for I/O interface circuit Grant 9,762,243 - Kumar , et al. September 12, 2	2017-09-12
Driver circuit including driver transistors with controlled body biasing Grant 9,473,135 - Garg , et al. October 18, 2	2016-10-18
CMOS Schmitt trigger circuit and associated methods Grant 9,467,125 - Kumar , et al. October 11, 2	2016-10-11
Programmable hysteresis comparator Grant 9,397,622 - Vashishtha , et al. July 19, 2	2016-07-19
Cmos Schmitt Trigger Circuit And Associated Methods App 20160182022 - KUMAR; Vinod ; et al.	2016-06-23
Programmable Hysteresis Comparator App 20160126909 - Vashishtha; Sameer ; et al.	2016-05-05
Apparatus for Reference Voltage Generation for I/O Interface Circuit App 20160118986 - Kumar; Vinod ; et al.	2016-04-28
Driver Circuit Including Driver Transistors With Controlled Body Biasing App 20160094217 - Garg; Paras ; et al.	2016-03-31
Buffer circuit with reduced static leakage through controlled body biasing in FDSOI technology Grant 9,264,045 - Vashishtha , et al. February 16, 2	2016-02-16
Buffer Circuit With Reduced Static Leakage Through Controlled Body Biasing In Fdsoi Technology App 20150280716 - Vashishtha; Sameer ; et al.	2015-10-01
Operating conditions compensation circuit Grant 8,981,817 - Kumar , et al. March 17, 2	2015-03-17
Operating Conditions Compensation Circuit App 20140375357 - KUMAR; Vinod ; et al.	2014-12-25
Level shifter Grant 8,531,227 - Kumar , et al. September 10, 2	2013-09-10
Reduction of signal skew Grant 8,253,437 - Garg , et al. August 28, 2	2012-08-28
Architecture for efficient usage of IO Grant 8,207,754 - Garg , et al. June 26, 2	2012-06-26
Level Shifter App 20120013386 - Kumar; Vinod ; et al.	2012-01-19
Architecture For Efficient Usage Of Io App 20100213980 - Garg; Paras ; et al.	2010-08-26
Reduction Of Signal Skew App 20090167363 - Garg; Paras ; et al.	2009-07-02

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