Patent | Date |
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Integrated circuit air bridge structures and methods of fabricating same Grant 6,492,705 - Begley , et al. December 10, 2 | 2002-12-10 |
Silicon-glass bonded wafers Grant 5,994,204 - Young , et al. November 30, 1 | 1999-11-30 |
High frequency analog transistors, method of fabrication and circuit implementation Grant 5,892,264 - Davis , et al. April 6, 1 | 1999-04-06 |
High frequency analog transistors method of fabrication and circuit implementation Grant 5,807,780 - Davis , et al. September 15, 1 | 1998-09-15 |
Silicon-glass bonded wafers Grant 5,729,038 - Young , et al. March 17, 1 | 1998-03-17 |
High frequency analog transistors, method of fabrication and circuit implementation Grant 5,668,397 - Davis , et al. September 16, 1 | 1997-09-16 |
Sub-micron bonded SOI by trench planarization Grant 5,585,661 - McLachlan , et al. December 17, 1 | 1996-12-17 |
Method for forming recessed oxide isolation containing deep and shallow trenches Grant 5,504,033 - Bajor , et al. April 2, 1 | 1996-04-02 |
Methods for forming a transistor having an emitter with enhanced efficiency Grant 5,395,774 - Bajor , et al. March 7, 1 | 1995-03-07 |
Method for forming recessed oxide isolation containing deep and shallow trenches Grant 5,382,541 - Bajor , et al. January 17, 1 | 1995-01-17 |
Double level conductor structure Grant 5,066,995 - Young , et al. November 19, 1 | 1991-11-19 |
Vertical contact structure Grant 4,914,501 - Rivoli , et al. April 3, 1 | 1990-04-03 |
Radiation hardened complementary transistor integrated circuits Grant 4,903,108 - Young , et al. February 20, 1 | 1990-02-20 |
Process for the fabrication of a vertical contact Grant 4,851,257 - Young , et al. July 25, 1 | 1989-07-25 |
ESD protection transistors Grant 4,760,433 - Young , et al. July 26, 1 | 1988-07-26 |
Photoresist tapering process Grant 4,705,597 - Gimpelson , et al. November 10, 1 | 1987-11-10 |
Via metallization using metal fillets Grant 4,666,737 - Gimpelson , et al. May 19, 1 | 1987-05-19 |
Critical dimension measurement structure Grant 4,566,192 - Hankins , et al. January 28, 1 | 1986-01-28 |
Method of fabricating self-aligned bipolar transistor process and device utilizing etching and self-aligned masking Grant 4,269,636 - Rivoli , et al. May 26, 1 | 1981-05-26 |
High voltage CMOS with local oxidation for self-aligned guard rings and process of fabrication Grant 4,223,334 - Gasner , et al. September 16, 1 | 1980-09-16 |
Process for fabricating high voltage CMOS with self-aligned guard rings utilizing selective diffusion and local oxidation Grant 4,135,955 - Gasner , et al. January 23, 1 | 1979-01-23 |