| Patent | Date |
|---|
Semiconductor Devices And Methods For Fabricating The Same
App 20220285493 - Kim; Mun Hyeon ; et al. | 2022-09-08 |
Field-effect transistors (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals, and related complementary metal oxide semiconductor (CMOS) circuits
Grant 11,437,379 - Song , et al. September 6, 2 | 2022-09-06 |
Hybrid conductor integration in power rail
Grant 11,302,638 - Zhu , et al. April 12, 2 | 2022-04-12 |
Field-effect Transistors (fet) Circuits Employing Topside And Backside Contacts For Topside And Backside Routing Of Fet Power And Logic Signals, And Related Complementary Metal Oxide Semiconductor (cmos) Circuits
App 20220093594 - SONG; Stanley Seungchul ; et al. | 2022-03-24 |
Gate-all-around (GAA) transistors with additional bottom channel for reduced parasitic capacitance and methods of fabrication
Grant 11,257,917 - Yuan , et al. February 22, 2 | 2022-02-22 |
Gate-all-around (gaa) Transistors With Shallow Source/drain Regions And Methods Of Fabricating The Same
App 20220037493 - Feng; Peijie ; et al. | 2022-02-03 |
Gate-all-around (gaa) Transistors With Additional Bottom Channel For Reduced Parasitic Capacitance And Methods Of Fabrication
App 20210384310 - Yuan; Jun ; et al. | 2021-12-09 |
Cell circuits formed in circuit cells employing offset gate cut areas in a non-active area for routing transistor gate cross-connections
Grant 11,152,347 - Song , et al. October 19, 2 | 2021-10-19 |
Field effect transistor (FET) comprising channels with silicon germanium (SiGe)
Grant 11,145,654 - Lim , et al. October 12, 2 | 2021-10-12 |
Hybrid metallization interconnects for power distribution and signaling
Grant 11,121,075 - Badaroglu , et al. September 14, 2 | 2021-09-14 |
Hybrid Conductor Integration In Power Rail
App 20210217699 - ZHU; John Jianhong ; et al. | 2021-07-15 |
Shunt power rail with short line effect
Grant 11,038,344 - Zhu , et al. June 15, 2 | 2021-06-15 |
FIELD EFFECT TRANSISTOR (FET) COMPRISING CHANNELS WITH SILICON GERMANIUM (SiGe)
App 20210118883 - LIM; Kwanyong ; et al. | 2021-04-22 |
Dielectric isolated fin with improved fin profile
Grant 10,892,364 - Cheng , et al. January 12, 2 | 2021-01-12 |
Semiconductor structures having increased channel strain using fin release in gate regions
Grant 10,886,385 - Cheng , et al. January 5, 2 | 2021-01-05 |
Offset gate contact
Grant 10,854,604 - Kuo , et al. December 1, 2 | 2020-12-01 |
Circuits Having A Diffusion Break With Avoided Or Reduced Adjacent Semiconductor Channel Strain Relaxation, And Related Methods
App 20200303550 - Song; Stanley Seungchul ; et al. | 2020-09-24 |
Circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation, and related methods
Grant 10,763,364 - Song , et al. Sep | 2020-09-01 |
Circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation, and related methods
Grant 10,700,204 - Song , et al. | 2020-06-30 |
SELF-ALIGNED QUADRUPLE PATTERNING PROCESS FOR FIN PITCH BELOW 20nm
App 20200161189 - SONG; Stanley ; et al. | 2020-05-21 |
MIDDLE-OF-LINE (MOL) COMPLEMENTARY POWER RAIL(S) IN INTEGRATED CIRCUITS (ICs) FOR REDUCED SEMICONDUCTOR DEVICE RESISTANCE
App 20200105670 - Zhu; John Jianhong ; et al. | 2020-04-02 |
Standard cell architecture with M1 layer unidirectional routing
Grant 10,593,700 - Gupta , et al. | 2020-03-17 |
Dielectric Isolated Fin With Improved Fin Profile
App 20200083374 - Cheng; Kangguo ; et al. | 2020-03-12 |
Circuits Having A Diffusion Break With Avoided Or Reduced Adjacent Semiconductor Channel Strain Relaxation, And Related Methods
App 20200058792 - Song; Stanley Seungchul ; et al. | 2020-02-20 |
Self-aligned quadruple patterning process for Fin pitch below 20nm
Grant 10,559,501 - Song , et al. Feb | 2020-02-11 |
Shunt Power Rail With Short Line Effect
App 20200044440 - ZHU; John Jianhong ; et al. | 2020-02-06 |
Dielectric isolated fin with improved fin profile
Grant 10,546,955 - Cheng , et al. Ja | 2020-01-28 |
Integrated Circuits Employing Varied Gate Topography Between An Active Gate Region(s) And A Field Gate Region(s) In A Gate(s) Fo
App 20200020688 - Badaroglu; Mustafa ; et al. | 2020-01-16 |
Integrated Circuits (ics) Made Using Extreme Ultraviolet (euv) Patterning And Methods For Fabricating Such Ics
App 20200006122 - Badaroglu; Mustafa ; et al. | 2020-01-02 |
Cell Circuits Formed In Circuit Cells Employing Offset Gate Cut Areas In A Non-active Area For Routing Transistor Gate Cross-con
App 20190319022 - Song; Stanley Seungchul ; et al. | 2019-10-17 |
Integrated circuits including a FinFET and a nanostructure FET
Grant 10,439,039 - Song , et al. O | 2019-10-08 |
Hybrid Metal Interconnect Structures For Advanced Process Nodes
App 20190304919 - ZHU; John ; et al. | 2019-10-03 |
Hybrid Metallization Interconnects For Power Distribution And Signaling
App 20190295942 - BADAROGLU; Mustafa ; et al. | 2019-09-26 |
Systems And Methods For Dummy Gate Tie-offs In A Self-aligned Gate Contact (sagc) Cell
App 20190296126 - Song; Stanley Seungchul ; et al. | 2019-09-26 |
Integrated circuits employing a field gate(s) without dielectric layers and/or work function metal layers for reduced gate layout parasitic resistance, and related methods
Grant 10,411,091 - Badaroglu , et al. Sept | 2019-09-10 |
Semiconductor Structures Having Increased Channel Strain Using Fin Release In Gate Regions
App 20190237561 - Cheng; Kangguo ; et al. | 2019-08-01 |
Semiconductor structures having increased channel strain using fin release in gate regions
Grant 10,347,752 - Cheng , et al. July 9, 2 | 2019-07-09 |
Integrating a gate-all-around (GAA) field-effect transistor(s) (FET(S)) and a finFET(s) on a common substrate of a semiconductor die
Grant 10,332,881 - Badaroglu , et al. | 2019-06-25 |
Layout effect mitigation in FinFET
Grant 10,181,403 - Yang , et al. Ja | 2019-01-15 |
Hybrid coloring methodology for multi-pattern technology
Grant 10,175,571 - Chen , et al. J | 2019-01-08 |
Semiconductor device having an airgap defined at least partially by a protective structure
Grant 10,163,792 - Zhu , et al. Dec | 2018-12-25 |
Semiconductor devices employing field effect transistors (FETs) with multiple channel structures without shallow trench isolation (STI) void-induced electrical shorts
Grant 10,141,305 - Xu , et al. Nov | 2018-11-27 |
Fin field effect transistor (FET) (FinFET) complementary metal oxide semiconductor (CMOS) circuits employing single and double diffusion breaks for increased performance
Grant 10,134,734 - Yuan , et al. November 20, 2 | 2018-11-20 |
Semiconductor device having a gap defined therein
Grant 10,079,293 - Xu , et al. September 18, 2 | 2018-09-18 |
Semiconductor structures having increased channel strain using fin release in gate regions
Grant 10,056,474 - Cheng , et al. August 21, 2 | 2018-08-21 |
Layout Effect Mitigation In Finfet
App 20180197743 - YANG; Da ; et al. | 2018-07-12 |
Transistor temperature sensing
Grant 10,018,515 - Liu , et al. July 10, 2 | 2018-07-10 |
Method for mitigating layout effect in FINFET
Grant 9,997,360 - Yang , et al. June 12, 2 | 2018-06-12 |
Structure and method for compressively strained silicon germanium fins for pFET devices and tensily strained silicon fins for nFET devices
Grant 9,997,540 - Cheng , et al. June 12, 2 | 2018-06-12 |
Variable interconnect pitch for improved performance
Grant 9,984,029 - Rim , et al. May 29, 2 | 2018-05-29 |
Semiconductor Structures Having Increased Channel Strain Using Fin Release In Gate Regions
App 20180130894 - CHENG; Kangguo ; et al. | 2018-05-10 |
Strain release in pFET regions
Grant 9,966,387 - Cheng , et al. May 8, 2 | 2018-05-08 |
Dielectric Isolated Fin With Improved Fin Profile
App 20180122944 - Cheng; Kangguo ; et al. | 2018-05-03 |
Standard Cell Architecture With M1 Layer Unidirectional Routing
App 20180122824 - GUPTA; Mukul ; et al. | 2018-05-03 |
Semiconductor Device Having A Gap Defined Therein
App 20180114848 - Xu; Jeffrey Junhao ; et al. | 2018-04-26 |
Semiconductor structures having increased channel strain using fin release in gate regions
Grant 9,954,083 - Cheng , et al. April 24, 2 | 2018-04-24 |
NOVEL SELF-ALIGNED QUADRUPLE PATTERNING PROCESS FOR FIN PITCH BELOW 20nm
App 20180082906 - SONG; Stanley ; et al. | 2018-03-22 |
Layout Effect Mitigation In Finfet
App 20180082846 - YANG; Da ; et al. | 2018-03-22 |
SEMICONDUCTOR DEVICES EMPLOYING FIELD EFFECT TRANSISTORS (FETs) WITH MULTIPLE CHANNEL STRUCTURES WITHOUT SHALLOW TRENCH ISOLATION (STI) VOID-INDUCED ELECTRICAL SHORTS
App 20180076197 - Xu; Jeffrey Junhao ; et al. | 2018-03-15 |
Dielectric isolated fin with improved fin profile
Grant 9,917,188 - Cheng , et al. March 13, 2 | 2018-03-13 |
Trench metal insulator metal capacitor with oxygen gettering layer
Grant 9,911,597 - Ando , et al. March 6, 2 | 2018-03-06 |
Preventing buried oxide gouging during planar and FinFET processing on SOI
Grant 9,911,663 - Rim , et al. March 6, 2 | 2018-03-06 |
Standard cell architecture with M1 layer unidirectional routing
Grant 9,887,209 - Gupta , et al. February 6, 2 | 2018-02-06 |
Static random access memory (SRAM) bit cells with wordline landing pads split across boundary edges of the SRAM bit cells
Grant 9,876,017 - Mojumder , et al. January 23, 2 | 2018-01-23 |
Semiconductor device having a gap defined therein
Grant 9,871,121 - Xu , et al. January 16, 2 | 2018-01-16 |
Fin Field Effect Transistor (fet) (finfet) Complementary Metal Oxide Semiconductor (cmos) Circuits Employing Single And Double Diffusion Breaks For Increased Performance
App 20180006035 - Yuan; Jun ; et al. | 2018-01-04 |
Device and method to connect gate regions separated using a gate cut
Grant 9,853,112 - Liu , et al. December 26, 2 | 2017-12-26 |
Heterogeneous Cell Array
App 20170338215 - Song; Stanley Seungchul ; et al. | 2017-11-23 |
Static random access memory (SRAM) bit cells with wordlines on separate metal layers for increased performance, and related methods
Grant 9,806,083 - Mojumder , et al. October 31, 2 | 2017-10-31 |
Self-aligned structure
Grant 9,799,560 - Song , et al. October 24, 2 | 2017-10-24 |
Integrated Circuits Including A Finfet And A Nanostructure Fet
App 20170278842 - Song; Stanley Seungchul ; et al. | 2017-09-28 |
Strain release in PFET regions
Grant 9,761,610 - Cheng , et al. September 12, 2 | 2017-09-12 |
Trench Metal Insulator Metal Capacitor With Oxygen Gettering Layer
App 20170250073 - Ando; Takashi ; et al. | 2017-08-31 |
Dummy gate structure for electrical isolation of a fin DRAM
Grant 9,741,722 - Barth, Jr. , et al. August 22, 2 | 2017-08-22 |
Fin With An Epitaxial Cladding Layer
App 20170236841 - Song; Stanley Seungchul ; et al. | 2017-08-17 |
Partially dielectric isolated fin-shaped field effect transistor (FinFET)
Grant 9,735,277 - Cheng , et al. August 15, 2 | 2017-08-15 |
Dynamic random access memory cell with self-aligned strap
Grant 9,735,162 - Barth, Jr. , et al. August 15, 2 | 2017-08-15 |
NANOWIRE METAL-OXIDE SEMICONDUCTOR (MOS) FIELD-EFFECT TRANSISTORS (FETs) (MOSFETs) EMPLOYING A NANOWIRE CHANNEL STRUCTURE EMPLOYING RECESSED CONDUCTIVE STRUCTURES FOR CONDUCTIVELY COUPLING NANOWIRE STRUCTURES
App 20170207313 - Song; Stanley Seungchul ; et al. | 2017-07-20 |
Partially Dielectric Isolated Fin-shaped Field Effect Transistor (finfet)
App 20170170323 - Cheng; Kangguo ; et al. | 2017-06-15 |
NANOWIRE METAL-OXIDE SEMICONDUCTOR (MOS) FIELD-EFFECT TRANSISTORS (FETs) (MOSFETs) EMPLOYING A NANOWIRE CHANNEL STRUCTURE HAVING ROUNDED NANOWIRE STRUCTURES
App 20170170268 - Song; Stanley Seungchul ; et al. | 2017-06-15 |
Methods of forming fin isolation regions on FinFET semiconductor devices by implantation of an oxidation-retarding material
Grant 9,673,083 - Jacob , et al. June 6, 2 | 2017-06-06 |
Preventing Buried Oxide Gouging During Planar And Finfet Processing On Soi
App 20170148688 - Rim; Kern ; et al. | 2017-05-25 |
Voltage scaling for holistic energy management
Grant 9,660,649 - Mojumder , et al. May 23, 2 | 2017-05-23 |
Middle-of-line integration methods and semiconductor devices
Grant 9,653,399 - Zhu , et al. May 16, 2 | 2017-05-16 |
Trench metal-insulator-metal capacitor with oxygen gettering layer
Grant 9,653,534 - Ando , et al. May 16, 2 | 2017-05-16 |
Structure and method to make strained FinFET with improved junction capacitance and low leakage
Grant 9,653,541 - Cheng , et al. May 16, 2 | 2017-05-16 |
STRUCTURE AND METHOD FOR COMPRESSIVELY STRAINED SILICON GERMANIUM FINS FOR pFET DEVICES AND TENSILY STRAINED SILICON FINS FOR nFET DEVICES
App 20170125447 - Cheng; Kangguo ; et al. | 2017-05-04 |
Compact model for device/circuit/chip leakage current (IDDQ) calculation including process induced uplift factors
Grant 9,639,652 - Chang , et al. May 2, 2 | 2017-05-02 |
Preventing buried oxide gouging during planar and FinFET processing on SOI
Grant 9,634,090 - Rim , et al. April 25, 2 | 2017-04-25 |
High density area efficient thin-oxide decoupling capacitor using conductive gate resistor
Grant 9,633,996 - Ge , et al. April 25, 2 | 2017-04-25 |
Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via, and related methods
Grant 9,620,454 - Zhu , et al. April 11, 2 | 2017-04-11 |
Transistor Temperature Sensing
App 20170074728 - Liu; Yanxiang ; et al. | 2017-03-16 |
Multi-cell Transistor Device And Method Of Making Same With Cut Polyoxide Process For Self-aligned Contacts
App 20170077090 - SONG; Stanley Seungchul ; et al. | 2017-03-16 |
Structure and method for advanced bulk fin isolation
Grant 9,583,492 - Cheng , et al. February 28, 2 | 2017-02-28 |
Semiconductor Structures Having Increased Channel Strain Using Fin Release In Gate Regions
App 20170053839 - Cheng; Kangguo ; et al. | 2017-02-23 |
Strain Release In Pfet Regions
App 20170053943 - Cheng; Kangguo ; et al. | 2017-02-23 |
Semiconductor Structures Having Increased Channel Strain Using Fin Release In Gate Regions
App 20170053994 - Cheng; Kangguo ; et al. | 2017-02-23 |
FinFET and nanowire semiconductor devices with suspended channel regions and gate structures surrounding the suspended channel regions
Grant 9,577,100 - Cheng , et al. February 21, 2 | 2017-02-21 |
Dielectric Isolated Fin With Improved Fin Profile
App 20170040452 - Cheng; Kangguo ; et al. | 2017-02-09 |
Dummy gate structure for electrical isolation of a fin DRAM
Grant 9,564,445 - Barth, Jr. , et al. February 7, 2 | 2017-02-07 |
Structure and method for advanced bulk fin isolation
Grant 9,564,439 - Cheng , et al. February 7, 2 | 2017-02-07 |
Dynamic random access memory cell with self-aligned strap
Grant 9,564,443 - Barth, Jr. , et al. February 7, 2 | 2017-02-07 |
Device And Method To Connect Gate Regions Separated Using A Gate Cut
App 20170018620 - Liu; Yanxiang ; et al. | 2017-01-19 |
Structure and method for compressively strained silicon germanium fins for pFET devices and tensily strained silicon fins for nFET devices
Grant 9,548,386 - Cheng , et al. January 17, 2 | 2017-01-17 |
Dielectric isolated fin with improved fin profile
Grant 9,548,213 - Cheng , et al. January 17, 2 | 2017-01-17 |
Strain release in PFET regions
Grant 9,543,323 - Cheng , et al. January 10, 2 | 2017-01-10 |
User experience based management technique for mobile system-on-chips
Grant 9,542,518 - Mojumder , et al. January 10, 2 | 2017-01-10 |
Partially dielectric isolated fin-shaped field effect transistor (FinFET)
Grant 9,537,011 - Cheng , et al. January 3, 2 | 2017-01-03 |
Structure for preventing buried oxide gouging during planar and FinFET Processing on SOI
Grant 9,530,659 - Rim , et al. December 27, 2 | 2016-12-27 |
Hybrid Coloring Methodology For Multi-pattern Technology
App 20160370699 - CHEN; Xiangdong ; et al. | 2016-12-22 |
Strain Release In Pfet Regions
App 20160359003 - Cheng; Kangguo ; et al. | 2016-12-08 |
Conductive layer routing
Grant 9,508,589 - Song , et al. November 29, 2 | 2016-11-29 |
Structure For Coupling Metal Layer Interconnects In A Semiconductor Device
App 20160343661 - GUPTA; Mukul ; et al. | 2016-11-24 |
Half node scaling for vertical structures
Grant 9,478,541 - Song , et al. October 25, 2 | 2016-10-25 |
Capacitor from second level middle-of-line layer in combination with decoupling capacitors
Grant 9,478,490 - Zhu , et al. October 25, 2 | 2016-10-25 |
Systems and methods of forming a reduced capacitance device
Grant 9,472,453 - Xu , et al. October 18, 2 | 2016-10-18 |
Self-aligned Structure
App 20160293485 - Song; Stanley Seungchul ; et al. | 2016-10-06 |
Shared global read and write word lines
Grant 9,455,026 - Mojumder , et al. September 27, 2 | 2016-09-27 |
Methods of forming fin isolation regions on FinFET semiconductor devices using an oxidation-blocking layer of material and by performing a fin-trimming process
Grant 9,431,306 - Jacob , et al. August 30, 2 | 2016-08-30 |
Preventing Buried Oxide Gouging During Planar And Finfet Processing On Soi
App 20160247877 - Rim; Kern ; et al. | 2016-08-25 |
Middle-of-line Integration Methods And Semiconductor Devices
App 20160240485 - Zhu; John Jianhong ; et al. | 2016-08-18 |
Dielectric Isolated Fin With Improved Fin Profile
App 20160233315 - Cheng; Kangguo ; et al. | 2016-08-11 |
Methods Of Forming Fin Isolation Regions On Finfet Semiconductor Devices Using An Oxidation-blocking Layer Of Material And By Performing A Fin-trimming Process
App 20160225677 - Jacob; Ajey Poovannummoottil ; et al. | 2016-08-04 |
Methods Of Forming Fin Isolation Regions On Finfet Semiconductor Devices By Implantation Of An Oxidation-retarding Material
App 20160225659 - Jacob; Ajey Poovannummoottil ; et al. | 2016-08-04 |
Strain Release In Pfet Regions
App 20160204131 - Cheng; Kangguo ; et al. | 2016-07-14 |
Structure And Method For Advanced Bulk Fin Isolation
App 20160197078 - Cheng; Kangguo ; et al. | 2016-07-07 |
Structure And Method For Advanced Bulk Fin Isolation
App 20160197077 - Cheng; Kangguo ; et al. | 2016-07-07 |
Grounding dummy gate in scaled layout design
Grant 9,379,058 - Song , et al. June 28, 2 | 2016-06-28 |
Trench Metal-insulator-metal Capacitor With Oxygen Gettering Layer
App 20160181353 - Ando; Takashi ; et al. | 2016-06-23 |
Static Random Access Memory (sram) Bit Cells With Wordlines On Separate Metal Layers For Increased Performance, And Related Methods
App 20160163713 - Mojumder; Niladri Narayan ; et al. | 2016-06-09 |
Static Random Access Memory (sram) Bit Cells With Wordline Landing Pads Split Across Boundary Edges Of The Sram Bit Cells
App 20160163714 - Mojumder; Niladri Narayan ; et al. | 2016-06-09 |
Semiconductor device including dielectrically isolated finFETs and buried stressor
Grant 9,362,400 - Cheng , et al. June 7, 2 | 2016-06-07 |
Methods of forming fin isolation regions on finFET semiconductor devices using an oxidation-blocking layer of material
Grant 9,349,658 - Jacob , et al. May 24, 2 | 2016-05-24 |
Voltage Scaling For Holistic Energy Management
App 20160142054 - Mojumder; Niladri Narayan ; et al. | 2016-05-19 |
Shared Global Read And Write Word Lines
App 20160141021 - Mojumder; Niladri Narayan ; et al. | 2016-05-19 |
User Experience Based Management Technique For Mobile System-on-chips
App 20160140275 - Mojumder; Niladri Narayan ; et al. | 2016-05-19 |
Structure And Method To Make Strained Finfet With Improved Junction Capacitance And Low Leakage
App 20160133697 - Cheng; Kangguo ; et al. | 2016-05-12 |
Methods Of Forming A Metal-insulator-semiconductor (mis) Structure And A Dual Contact Device
App 20160126144 - Xu; Jeffrey Junhao ; et al. | 2016-05-05 |
Complex circuits utilizing fin structures
Grant 9,318,489 - Cheng , et al. April 19, 2 | 2016-04-19 |
Structure and method for advanced bulk fin isolation
Grant 9,299,618 - Cheng , et al. March 29, 2 | 2016-03-29 |
Structure And Method For Advanced Bulk Fin Isolation
App 20160086858 - Cheng; Kangguo ; et al. | 2016-03-24 |
Metal-gate With An Amorphous Metal Layer
App 20160086805 - Xu; Jeffrey Junhao ; et al. | 2016-03-24 |
Finfet with oxidation-induced stress
Grant 9,293,583 - Cheng , et al. March 22, 2 | 2016-03-22 |
MIDDLE-OF-LINE (MOL) MANUFACTURED INTEGRATED CIRCUITS (ICs) EMPLOYING LOCAL INTERCONNECTS OF METAL LINES USING AN ELONGATED VIA, AND RELATED METHODS
App 20160079175 - Zhu; John Jianhong ; et al. | 2016-03-17 |
Tie-off Structures For Middle-of-line (mol) Manufactured Integrated Circuits, And Related Methods
App 20160079167 - Zhu; John Jianhong ; et al. | 2016-03-17 |
Capacitor From Second Level Middle-of-line Layer In Combination With Decoupling Capacitors
App 20160071795 - ZHU; John Jianhong ; et al. | 2016-03-10 |
Half Node Scaling For Vertical Structures
App 20160071847 - SONG; Stanley Seungchul ; et al. | 2016-03-10 |
Structure and method to make strained FinFET with improved junction capacitance and low leakage
Grant 9,276,113 - Cheng , et al. March 1, 2 | 2016-03-01 |
Silicon germanium FinFET formation by Ge condensation
Grant 9,257,556 - Xu , et al. February 9, 2 | 2016-02-09 |
Stress In N-channel Field Effect Transistors
App 20160035891 - XU; Jeffrey Junhao ; et al. | 2016-02-04 |
Dummy Gate Structure For Electrical Isolation Of A Fin Dram
App 20160027789 - Barth, JR.; John E. ; et al. | 2016-01-28 |
Semiconductor Device Having An Airgap Defined At Least Partially By A Protective Structure
App 20160027726 - Zhu; John Jianhong ; et al. | 2016-01-28 |
Dynamic Random Access Memory Cell With Self-aligned Strap
App 20160027788 - Barth, JR.; John E. ; et al. | 2016-01-28 |
Dielectric filler fins for planar topography in gate level
Grant 9,245,981 - Cheng , et al. January 26, 2 | 2016-01-26 |
Self-aligned Via For Gate Contact Of Semiconductor Devices
App 20160005822 - SONG; Stanley Seungchul ; et al. | 2016-01-07 |
Finfet And Nanowire Semiconductor Devices With Suspended Channel Regions And Gate Structures Surrounding The Suspended Channel Regions
App 20150364603 - Cheng; Kangguo ; et al. | 2015-12-17 |
Finfet With Oxidation-induced Stress
App 20150357470 - Cheng; Kangguo ; et al. | 2015-12-10 |
Fin field effect transistor with dielectric isolation and anchored stressor elements
Grant 9,209,094 - Cheng , et al. December 8, 2 | 2015-12-08 |
Complex Circuits Utilizing Fin Structures
App 20150340364 - Cheng; Kangguo ; et al. | 2015-11-26 |
Complex Circuits Utilizing Fin Structures
App 20150340291 - Cheng; Kangguo ; et al. | 2015-11-26 |
Via material selection and processing
Grant 9,196,583 - Zhu , et al. November 24, 2 | 2015-11-24 |
Dielectric Filler Fins For Planar Topography In Gate Level
App 20150333156 - Cheng; Kangguo ; et al. | 2015-11-19 |
Standard Cell Architecture With M1 Layer Unidirectional Routing
App 20150333008 - GUPTA; Mukul ; et al. | 2015-11-19 |
Complex circuits utilizing fin structures
Grant 9,190,329 - Cheng , et al. November 17, 2 | 2015-11-17 |
Via Material Selection And Processing
App 20150325515 - ZHU; John Jianhong ; et al. | 2015-11-12 |
Preventing Buried Oxide Gouging During Planar And Finfet Processing On Soi
App 20150318180 - Rim; Kern ; et al. | 2015-11-05 |
FinFET with oxidation-induced stress
Grant 9,178,068 - Cheng , et al. November 3, 2 | 2015-11-03 |
Variable Interconnect Pitch For Improved Performance
App 20150301973 - RIM; Kern ; et al. | 2015-10-22 |
Complementarily strained FinFET structure
Grant 9,165,929 - Rim , et al. October 20, 2 | 2015-10-20 |
Methods Of Forming A Metal-insulator-semiconductor (mis) Structure And A Dual Contact Device
App 20150270134 - Xu; Jeffrey Junhao ; et al. | 2015-09-24 |
Systems And Methods Of Forming A Reduced Capacitance Device
App 20150262875 - Xu; Jeffrey Junhao ; et al. | 2015-09-17 |
Structure And Method To Make Strained Finfet With Improved Junction Capacitance And Low Leakage
App 20150255606 - Cheng; Kangguo ; et al. | 2015-09-10 |
Semiconductor Device Having A Gap Defined Therein
App 20150255571 - Xu; Jeffrey Junhao ; et al. | 2015-09-10 |
Dielectric Isolated Fin With Improved Fin Profile
App 20150243755 - Cheng; Kangguo ; et al. | 2015-08-27 |
Methods of forming isolated germanium-containing fins for a FinFET semiconductor device
Grant 9,117,875 - Jacob , et al. August 25, 2 | 2015-08-25 |
Grounding Dummy Gate In Scaled Layout Design
App 20150235948 - SONG; Stanley Seungchul ; et al. | 2015-08-20 |
Structure And Process To Decouple Deep Trench Capacitors And Well Isolation
App 20150214244 - Ho; Herbert L. ; et al. | 2015-07-30 |
Dielectric filler fins for planar topography in gate level
Grant 9,093,534 - Cheng , et al. July 28, 2 | 2015-07-28 |
Dynamic Random Access Memory Cell With Self-aligned Strap
App 20150206884 - Barth, Jr.; John E. ; et al. | 2015-07-23 |
Dummy Gate Structure For Electrical Isolation Of A Fin Dram
App 20150206885 - Barth, Jr.; John E. ; et al. | 2015-07-23 |
Methods Of Forming Isolated Germanium-containing Fins For A Finfet Semiconductor Device
App 20150200128 - Jacob; Ajey Poovannummoottil ; et al. | 2015-07-16 |
Silicon Germanium Finfet Formation By Ge Condensation
App 20150194525 - XU; Jeffrey Junhao ; et al. | 2015-07-09 |
Conductive Layer Routing
App 20150194339 - SONG; Stanley Seungchul ; et al. | 2015-07-09 |
Techniques for quantifying fin-thickness variation in FINFET technology
Grant 9,064,739 - Haensch , et al. June 23, 2 | 2015-06-23 |
Structure and method for mobility enhanced MOSFETs with unalloyed silicide
Grant 9,059,316 - Liu , et al. June 16, 2 | 2015-06-16 |
Complementarily Strained Finfet Structure
App 20150144962 - RIM; Kern ; et al. | 2015-05-28 |
Method and structure for forming a localized SOI finFET
Grant 8,987,823 - Cheng , et al. March 24, 2 | 2015-03-24 |
Fin structure with varying isolation thickness
Grant 8,969,155 - Cheng , et al. March 3, 2 | 2015-03-03 |
Method and structure for pFET junction profile with SiGe channel
Grant 8,962,417 - Rim , et al. February 24, 2 | 2015-02-24 |
Dielectric Filler Fins For Planar Topography In Gate Level
App 20150028398 - Cheng; Kangguo ; et al. | 2015-01-29 |
Fin Field Effect Transistor With Dielectric Isolation And Anchored Stressor Elements
App 20150028419 - Cheng; Kangguo ; et al. | 2015-01-29 |
Techniques for quantifying fin-thickness variation in FINFET technology
Grant 8,940,558 - Haensch , et al. January 27, 2 | 2015-01-27 |
Strained finFET with an electrically isolated channel
Grant 8,928,086 - Utomo , et al. January 6, 2 | 2015-01-06 |
Strained Finfet With An Electrically Isolated Channel
App 20140377924 - Utomo; Henry K. ; et al. | 2014-12-25 |
Fin Structure With Varying Isolation Thickness
App 20140332861 - Cheng; Kangguo ; et al. | 2014-11-13 |
Techniques for Quantifying Fin-Thickness Variation in FINFET Technology
App 20140266254 - Haensch; Wilfried E.A. ; et al. | 2014-09-18 |
Techniques for Quantifying Fin-Thickness Variation in FINFET Technology
App 20140273298 - Haensch; Wilfried E.A. ; et al. | 2014-09-18 |
METHOD AND STRUCTURE FOR pFET JUNCTION PROFILE WITH SiGe CHANNEL
App 20140273381 - Rim; Kern ; et al. | 2014-09-18 |
Strained Finfet With An Electrically Isolated Channel
App 20140191297 - Utomo; Henry K. ; et al. | 2014-07-10 |
Method and structure for forming a localized SOI finFET
Grant 8,766,363 - Cheng , et al. July 1, 2 | 2014-07-01 |
Method And Structure For Forming A Localized Soi Finfet
App 20140124860 - Cheng; Kangguo ; et al. | 2014-05-08 |
Method And Structure For Forming A Localized Soi Finfet
App 20140124863 - Cheng; Kangguo ; et al. | 2014-05-08 |
Compact Model For Device/circuit/chip Leakage Current (iddq) Calculation Including Process Induced Uplift Factors
App 20140123097 - Chang; Paul ; et al. | 2014-05-01 |
Method and structure for pFET junction profile with SiGe channel
Grant 8,659,054 - Rim , et al. February 25, 2 | 2014-02-25 |
Substantially L-shaped silicide for contact
Grant 8,643,119 - Luo , et al. February 4, 2 | 2014-02-04 |
Structure and method for mobility enhanced MOSFETS with unalloyed silicide
Grant 8,642,434 - Liu , et al. February 4, 2 | 2014-02-04 |
Compact model for device/circuit/chip leakage current (IDDQ) calculation including process induced uplift factors
Grant 8,626,480 - Chang , et al. January 7, 2 | 2014-01-07 |
Formation of improved SOI substrates using bulk semiconductor wafers
Grant 8,268,698 - Henson , et al. September 18, 2 | 2012-09-18 |
Structure and method for mobility enhanced MOSFETs with unalloyed silicide
Grant 8,217,423 - Liu , et al. July 10, 2 | 2012-07-10 |
Structure And Method For Mobility Enhanced Mosfets With Unalloyed Silicide
App 20120149159 - Liu; Yaocheng ; et al. | 2012-06-14 |
Structure And Method For Mobility Enhanced Mosfets With Unalloyed Silicide
App 20120146092 - Liu; Yaocheng ; et al. | 2012-06-14 |
Method and Structure for pFET Junction Profile With SiGe Channel
App 20120091506 - Rim; Kern ; et al. | 2012-04-19 |
Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
Grant 8,017,499 - Chan , et al. September 13, 2 | 2011-09-13 |
Method and apparatus for post silicide spacer removal
Grant 7,977,185 - Greene , et al. July 12, 2 | 2011-07-12 |
Formation Of Improved Soi Substrates Using Bulk Semiconductor Wafers
App 20110147885 - Henson; William K. ; et al. | 2011-06-23 |
Embedded stressor structure and process
Grant 7,939,413 - Chong , et al. May 10, 2 | 2011-05-10 |
Semiconductor structure and method of forming the structure
Grant 7,932,144 - Liu , et al. April 26, 2 | 2011-04-26 |
Formation of improved SOI substrates using bulk semiconductor wafers
Grant 7,932,158 - Henson , et al. April 26, 2 | 2011-04-26 |
Compact Model For Device/circuit/chip Leakage Current (iddq) Calculation Including Process Induced Uplift Factors
App 20110082680 - Chang; Paul ; et al. | 2011-04-07 |
MOSFET structure with multiple self-aligned silicide contacts
Grant 7,888,264 - Chan , et al. February 15, 2 | 2011-02-15 |
CMOS structure including differential channel stressing layer compositions
Grant 7,875,511 - Yaocheng , et al. January 25, 2 | 2011-01-25 |
Mosfet Structure With Multiple Self-aligned Silicide Contacts
App 20100304563 - Chan; Kevin K. ; et al. | 2010-12-02 |
Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon
Grant 7,838,932 - Chakravarti , et al. November 23, 2 | 2010-11-23 |
Ultra thin channel (UTC) MOSFET structure formed on BOX regions having different depths and different thicknesses beneath the UTC and source/drain regions and method of manufacture thereof
Grant 7,812,397 - Cheng , et al. October 12, 2 | 2010-10-12 |
Strained-silicon CMOS device and method
Grant 7,808,081 - Bryant , et al. October 5, 2 | 2010-10-05 |
Strained-silicon Cmos Device And Method
App 20100244139 - BRYANT; Andres ; et al. | 2010-09-30 |
High performance stress-enhance MOSFET and method of manufacture
Grant 7,791,144 - Chidambarrao , et al. September 7, 2 | 2010-09-07 |
Transistor with dielectric stressor elements
Grant 7,759,739 - Chidambarrao , et al. July 20, 2 | 2010-07-20 |
MOSFET structure with multiple self-aligned silicide contacts
Grant 7,737,032 - Chan , et al. June 15, 2 | 2010-06-15 |
Semiconductor structure and method of forming the structure
Grant 7,714,358 - Liu , et al. May 11, 2 | 2010-05-11 |
High-performance CMOS SOI devices on hybrid crystal-oriented substrates
Grant 7,713,807 - Doris , et al. May 11, 2 | 2010-05-11 |
Semiconductor Structure And Method Of Forming The Structure
App 20100112766 - Liu; Yaocheng ; et al. | 2010-05-06 |
Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance
Grant 7,682,915 - Chen , et al. March 23, 2 | 2010-03-23 |
Strained complementary metal oxide semiconductor (CMOS) on rotated wafers and methods thereof
Grant 7,675,055 - Ieong , et al. March 9, 2 | 2010-03-09 |
Transistor with dielectric stressor element fully underlying the active semiconductor region
Grant 7,659,581 - Chidambarrao , et al. February 9, 2 | 2010-02-09 |
High Performance Stress-enhance Mosfet And Method Of Manufacture
App 20100013024 - Chidambarrao; Dureseti ; et al. | 2010-01-21 |
Strained-silicon Cmos Device And Method
App 20090305474 - Bryant; Andres ; et al. | 2009-12-10 |
High performance stress-enhance MOSFET and method of manufacture
Grant 7,615,418 - Chidambarrao , et al. November 10, 2 | 2009-11-10 |
High performance stress-enhance MOSFET and method of manufacture
Grant 7,608,489 - Chidambarrao , et al. October 27, 2 | 2009-10-27 |
Dual metal integration scheme based on full silicidation of the gate electrode
Grant 7,605,077 - Henson , et al. October 20, 2 | 2009-10-20 |
Method and Structure For NFET With Embedded Silicon Carbon
App 20090181508 - Holt; Judson R. ; et al. | 2009-07-16 |
Silicon/silcion germaninum/silicon body device with embedded carbon dopant
Grant 7,560,326 - Mocuta , et al. July 14, 2 | 2009-07-14 |
Stress engineering using dual pad nitride with selective SOI device architecture
Grant 7,550,364 - Chidambarrao , et al. June 23, 2 | 2009-06-23 |
MOSFET structure with multiple self-aligned silicide contacts
Grant 7,528,067 - Chan , et al. May 5, 2 | 2009-05-05 |
Localized strain relaxation for strained Si directly on insulator
Grant 7,524,740 - Liu , et al. April 28, 2 | 2009-04-28 |
Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
Grant 7,507,989 - Chan , et al. March 24, 2 | 2009-03-24 |
Formation Of Improved Soi Substrates Using Bulk Semiconductor Wafers
App 20090039461 - Henson; William K. ; et al. | 2009-02-12 |
Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
Grant 7,485,518 - Chan , et al. February 3, 2 | 2009-02-03 |
Transistor having dielectric stressor elements at different depths from a semiconductor surface for applying shear stress
Grant 7,476,938 - Chidambarrao , et al. January 13, 2 | 2009-01-13 |
Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon
Grant 7,473,594 - Chakravarti , et al. January 6, 2 | 2009-01-06 |
Ultra Thin Channel (UTC) MOSFET Structure Formed on BOX Regions Having Different Depths and Different Thicknesses Beneath the UTC and SourceDrain Regions and Method of Manufacture Thereof
App 20080283918 - Cheng; Kangguo ; et al. | 2008-11-20 |
Substantially L-shaped Silicide For Contact And Related Method
App 20080283934 - Luo; Zhijiong ; et al. | 2008-11-20 |
Formation of improved SOI substrates using bulk semiconductor wafers
Grant 7,452,784 - Henson , et al. November 18, 2 | 2008-11-18 |
Mosfet Structure With Multiple Self-aligned Silicide Contacts
App 20080268600 - Chan; Kevin K. ; et al. | 2008-10-30 |
Method of forming substantially L-shaped silicide contact for a semiconductor device
Grant 7,442,619 - Luo , et al. October 28, 2 | 2008-10-28 |
HETERO-INTEGRATED STRAINED SILICON n- AND p- MOSFETS
App 20080251813 - Boyd; Diane C. ; et al. | 2008-10-16 |
Cmos Structure Including Differential Channel Stressing Layer Compositions
App 20080224218 - Liu; Yaocheng ; et al. | 2008-09-18 |
STRAINED Si MOSFET ON TENSILE-STRAINED SiGe-ON-INSULATOR (SGOI)
App 20080220588 - Chan; Kevin K. ; et al. | 2008-09-11 |
Pre-epitaxial Disposable Spacer Integration Scheme With Very Low Temperature Selective Epitaxy For Enhanced Device Performance
App 20080199998 - Chen; Huajie ; et al. | 2008-08-21 |
Semiconductor Structure And Method Of Forming The Structure
App 20080191243 - Liu; Yaocheng ; et al. | 2008-08-14 |
Structure And Method For Mobility Enhanced Mosfets With Unalloyed Silicide
App 20080164491 - Liu; Yaocheng ; et al. | 2008-07-10 |
Hetero-integrated strained silicon n- and p-MOSFETs
Grant 7,396,747 - Boyd , et al. July 8, 2 | 2008-07-08 |
Double silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structures
Grant 7,393,732 - Rim July 1, 2 | 2008-07-01 |
Raised Sti Structure And Superdamascene Technique For Nmosfet Performance Enhancement With Embedded Silicon Carbon
App 20080128712 - Chakravarti; Ashima B. ; et al. | 2008-06-05 |
Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance
Grant 7,381,623 - Chen , et al. June 3, 2 | 2008-06-03 |
High-performance Cmos Soi Devices On Hybrid Crystal-oriented Substrates
App 20080096330 - Doris; Bruce B. ; et al. | 2008-04-24 |
Strained complementary metal oxide semiconductor (CMOS) on rotated wafers and methods thereof
Grant 7,348,611 - Ieong , et al. March 25, 2 | 2008-03-25 |
STRAINED Si MOSFET ON TENSILE-STRAINED SiGe-ON-INSULATOR (SGOI)
App 20080042166 - Chan; Kevin K. ; et al. | 2008-02-21 |
Strained Complementary Metal Oxide Semiconductor (cmos) On Rotated Wafers And Methods Thereof
App 20080042215 - Ieong; Meikei ; et al. | 2008-02-21 |
High-performance CMOS devices on hybrid crystal oriented substrates
Grant 7,329,923 - Doris , et al. February 12, 2 | 2008-02-12 |
Raised Sti Structure And Superdamascene Technique For Nmosfet Performance Enhancement With Embedded Silicon Carbon
App 20080026516 - Chakravarti; Ashima B. ; et al. | 2008-01-31 |
HETERO-INTEGRATED STRAINED SILICON n- AND p- MOSFETS
App 20070278517 - Boyd; Diane C. ; et al. | 2007-12-06 |
Formation Of Improved Soi Substrates Using Bulk Semiconductor Wafers
App 20070275537 - Henson; William K. ; et al. | 2007-11-29 |
Optimized Deep Source/drain Junctions With Thin Poly Gate In A Field Effect Transistor
App 20070275532 - Chidambarrao; Dureseti ; et al. | 2007-11-29 |
Substantially L-shaped Silicide For Contact And Related Method
App 20070267753 - Luo; Zhijiong ; et al. | 2007-11-22 |
Fully silicided gate electrodes and method of making the same
Grant 7,297,618 - Henson , et al. November 20, 2 | 2007-11-20 |
Silicon/silcion Germaninum/silicon Body Device With Embedded Carbon Dopant
App 20070257249 - Mocuta; Anda C. ; et al. | 2007-11-08 |
High Performance Stress-enhance Mosfet And Method Of Manufacture
App 20070254422 - Chidambarrao; Dureseti ; et al. | 2007-11-01 |
High Performance Stress-enhance Mosfet And Method Of Manufacture
App 20070254423 - Chidambarrao; Dureseti ; et al. | 2007-11-01 |
Epitaxy of Silicon-Carbon Substitutional Solid Solutions by Ultra-Fast Annealing of Amorphous Material
App 20070238267 - Liu; Yaocheng ; et al. | 2007-10-11 |
CMOS process with Si gates for nFETs and SiGe gates for pFETs
App 20070235759 - Henson; William K. ; et al. | 2007-10-11 |
Dual Metal Integration Scheme Based On Full Silicidation Of The Gate Electrode
App 20070228458 - Henson; William K. ; et al. | 2007-10-04 |
Hetero-integrated strained silicon n- and p-MOSFETs
Grant 7,273,800 - Boyd , et al. September 25, 2 | 2007-09-25 |
Laser Surface Annealing Of Antimony Doped Amorphized Semiconductor Region
App 20070212861 - Chidambarrao; Dureseti ; et al. | 2007-09-13 |
Method And Apparatus For Post Silicide Spacer Removal
App 20070161244 - Greene; Brian J. ; et al. | 2007-07-12 |
STRAINED Si MOSFET ON TENSILE-STRAINED SiGe-ON-INSULATOR (SGOI)
App 20070155130 - Chan; Kevin K. ; et al. | 2007-07-05 |
Embedded stressor structure and process
App 20070132038 - Chong; Yung Fu ; et al. | 2007-06-14 |
Strained-silicon CMOS device and method
Grant 7,227,205 - Bryant , et al. June 5, 2 | 2007-06-05 |
Stress Engineering Using Dual Pad Nitride With Selective Soi Device Architecture
App 20070122965 - Chidambarrao; Dureseti ; et al. | 2007-05-31 |
Methods To Form Heterogeneous Silicides/germanides In Cmos Technology
App 20070123042 - Rim; Kern ; et al. | 2007-05-31 |
Transistor With Dielectric Stressor Element Fully Underlying The Active Semiconductor Region
App 20070122956 - Chidambarrao; Dureseti ; et al. | 2007-05-31 |
Transistor Having Dielectric Stressor Elements At Different Depths From A Semiconductor Surface For Applying Shear Stress
App 20070114632 - Chidambarrao; Dureseti ; et al. | 2007-05-24 |
Transistor having dielectric stressor elements for applying in-plane shear stress
Grant 7,221,024 - Chidambarrao , et al. May 22, 2 | 2007-05-22 |
Strained-silicon Cmos Device And Method
App 20070111417 - Bryant; Andres ; et al. | 2007-05-17 |
Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
Grant 7,217,949 - Chan , et al. May 15, 2 | 2007-05-15 |
Transistor Having Dielectric Stressor Elements For Applying In-plane Shear Stress
App 20070096223 - Chidambarrao; Dureseti ; et al. | 2007-05-03 |
Transistor With Dielectric Stressor Elements
App 20070096215 - Chidambarrao; Dureseti ; et al. | 2007-05-03 |
Mosfet Structure With Multiple Self-aligned Silicide Contacts
App 20070087536 - Chan; Kevin K. ; et al. | 2007-04-19 |
Stress engineering using dual pad nitride with selective SOI device architecture
Grant 7,202,513 - Chidambarrao , et al. April 10, 2 | 2007-04-10 |
Planar Ultra-thin Semiconductor-on-insulator Channel Mosfet With Embedded Source/drain
App 20070069300 - Cheng; Kangguo ; et al. | 2007-03-29 |
Stress Engineering Using Dual Pad Nitride With Selective Soi Device Architecture
App 20070069294 - Chidambarrao; Dureseti ; et al. | 2007-03-29 |
Compressive SiGe <110> growth and structure of MOSFET devices
Grant 7,187,059 - Chan , et al. March 6, 2 | 2007-03-06 |
Shallow trench isolation structure for strained Si on SiGe
Grant 7,183,175 - Koester , et al. February 27, 2 | 2007-02-27 |
Method For Forming A Sige Or Sigec Gate Selectively In A Complementary Mis/mos Fet Device
App 20060258073 - Greene; Brian Joseph ; et al. | 2006-11-16 |
Method for forming a SiGe or SiGeC gate selectively in a complementary MIS/MOS FET device
Grant 7,132,322 - Greene , et al. November 7, 2 | 2006-11-07 |
MOSFET structure with multiple self-aligned silicide contacts
Grant 7,129,548 - Chan , et al. October 31, 2 | 2006-10-31 |
Strained complementary metal oxide semiconductor (CMOS) on rotated wafers and methods thereof
App 20060237785 - Ieong; Meikei ; et al. | 2006-10-26 |
Double silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structures
App 20060125013 - Rim; Kern | 2006-06-15 |
Hetero-integrated strained silicon n-and p-MOSFETs
App 20060091377 - Boyd; Diane C. ; et al. | 2006-05-04 |
Double silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structures
Grant 7,034,362 - Rim April 25, 2 | 2006-04-25 |
MOSFET structure with high mechanical stress in the channel
Grant 7,002,209 - Chen , et al. February 21, 2 | 2006-02-21 |
MOSFET structure with multiple self-aligned silicide contacts
App 20060033165 - Chan; Kevin K. ; et al. | 2006-02-16 |
Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
App 20060001088 - Chan; Kevin K. ; et al. | 2006-01-05 |
Strained-silicon CMOS device and method
App 20050285187 - Bryant, Andres ; et al. | 2005-12-29 |
Compressive SiGe <110> growth and structure of MOSFET devices
App 20050285159 - Chan, Kevin K. ; et al. | 2005-12-29 |
Shallow trench isolation structure for strained Si on SiGe
App 20050260825 - Koester, Steven John ; et al. | 2005-11-24 |
MOSFET structure with high mechanical stress in the channel
App 20050260808 - Chen, Xiangdong ; et al. | 2005-11-24 |
Strained silicon CMOS on hybrid crystal orientations
App 20050236687 - Chan, Kevin K. ; et al. | 2005-10-27 |
Double silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structures
App 20050082531 - Rim, Kern | 2005-04-21 |
Method Of Forming Strained Silicon On Insulator
App 20050070070 - Rim, Kern | 2005-03-31 |
High-performance CMOS devices on hybrid crystal oriented substrates
App 20040256700 - Doris, Bruce B. ; et al. | 2004-12-23 |
Multiple gate MOSFET structure with strained Si Fin body
Grant 6,815,738 - Rim November 9, 2 | 2004-11-09 |
Multiple gate MOSFET structure with strained Si Fin body
App 20040169239 - Rim, Kern | 2004-09-02 |
Shallow trench isolation structure for strained Si on SiGe
App 20040164373 - Koester, Steven John ; et al. | 2004-08-26 |
Semiconductor-on-insulator lateral p-i-n photodetector with a reflecting mirror and backside contact and method for forming the same
Grant 6,667,528 - Cohen , et al. December 23, 2 | 2003-12-23 |
Strained silicon on insulator structures
Grant 6,603,156 - Rim August 5, 2 | 2003-08-05 |
Semiconductor-on-insulator lateral p-i-n photodetector with a reflecting mirror and backside contact and method for forming the same
App 20030122210 - Cohen, Guy Moshe ; et al. | 2003-07-03 |
Strained silicon on insulator structures
App 20020140031 - Rim, Kern | 2002-10-03 |
Methods for forming lateral trench optical detectors
Grant 6,451,702 - Yang , et al. September 17, 2 | 2002-09-17 |
Methods for forming lateral trench optical detectors
App 20020115300 - Yang, Min ; et al. | 2002-08-22 |
Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation
Grant 6,429,061 - Rim August 6, 2 | 2002-08-06 |
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