loadpatents
name:-0.022661924362183
name:-0.016555070877075
name:-0.00045919418334961
Riley; Mack Wayne Patent Filings

Riley; Mack Wayne

Patent Applications and Registrations

Patent applications and USPTO patent grants for Riley; Mack Wayne.The latest application filed is for "evaluation of multiple input signature register results".

Company Profile
0.16.21
  • Riley; Mack Wayne - Austin TX
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Evaluation of multiple input signature register results
Grant 9,336,105 - Riley May 10, 2
2016-05-10
Evaluation Of Multiple Input Signature Register Results
App 20120084603 - Riley; Mack Wayne
2012-04-05
Circuit to reduce transient current swings during mode transitions of high frequency/high power chips
Grant 7,831,006 - Boerstler , et al. November 9, 2
2010-11-09
Circuit to reduce power supply fluctuations in high frequency/high power circuits
Grant 7,809,974 - Boerstler , et al. October 5, 2
2010-10-05
Dynamic frequency scaling sequence for multi-gigahertz microprocessors
Grant 7,702,944 - Chelstrom , et al. April 20, 2
2010-04-20
Using a single bank of efuses to successively store testing data from multiple stages of testing
Grant 7,698,608 - Riley April 13, 2
2010-04-13
Method to gate off PLLS in a deep power saving state without separate clock distribution for power management logic
Grant 7,656,237 - Riley , et al. February 2, 2
2010-02-02
Method and apparatus for detecting frequency lock in a system including a frequency synthesizer
Grant 7,620,126 - Boerstler , et al. November 17, 2
2009-11-17
Information handling system capable of detecting frequency lock of signals downstream from a signal synthesized by frequency synthesizer
Grant 7,590,194 - Boerstler , et al. September 15, 2
2009-09-15
Structure For An Integrated Circuit That Employs Multiple Interfaces
App 20090222251 - Gloekler; Tilman ;   et al.
2009-09-03
System and method for advanced logic built-in self test with selection of scan channels
Grant 7,546,504 - Riley , et al. June 9, 2
2009-06-09
Maintaining Circuit Delay Characteristics During Power Management Mode
App 20090121747 - Dhong; Sang Hoo ;   et al.
2009-05-14
Dynamic Frequency Scaling Sequence for Multi-Gigahertz Microprocessors
App 20090119552 - Chelstrom; Nathan ;   et al.
2009-05-07
Dynamic frequency scaling sequence for multi-gigahertz microprocessors
Grant 7,516,350 - Chelstrom , et al. April 7, 2
2009-04-07
Method to Bridge a Distance Between eFuse Banks That Contain Encoded Data
App 20090058503 - Genden; Michael Joseph ;   et al.
2009-03-05
Systems and methods for LBIST testing using isolatable scan chains
Grant 7,484,153 - Kiryu , et al. January 27, 2
2009-01-27
Circuit to Reduce Transient Current Swings During Mode Transitions of High Frequency/High Power Chips
App 20080272820 - Boerstler; David William ;   et al.
2008-11-06
Method to reduce transient current swings during mode transitions of high frequency/high power chips
Grant 7,430,264 - Boerstler , et al. September 30, 2
2008-09-30
Method And Apparatus For Interfacing To An Integrated Circuit That Employs Multiple Interfaces
App 20080147901 - Gloekler; Tilman ;   et al.
2008-06-19
Circuit to Reduce Power Supply Fluctuations in High Frequency/High Power Circuits
App 20080133957 - Boerstler; David William ;   et al.
2008-06-05
Apparatus and method for using a single bank of eFuses to successively store testing data from multiple stages of testing
Grant 7,373,573 - Riley May 13, 2
2008-05-13
Apparatus and Method for Using a Single Bank of eFuses to Successively Store Testing Data from Multiple Stages of Testing
App 20080104469 - Riley; Mack Wayne
2008-05-01
Circuit to reduce power supply fluctuations in high frequency/ high power circuits
Grant 7,350,096 - Boerstler , et al. March 25, 2
2008-03-25
System and Method for Advanced Logic Built-in Self Test with Selection of Scan Channels
App 20080052579 - Riley; Mack Wayne ;   et al.
2008-02-28
Deep power saving by disabling clock distribution without separate clock distribution for power management logic
Grant 7,284,138 - Riley , et al. October 16, 2
2007-10-16
Systems and methods for LBIST testing using commonly controlled LBIST satellites
App 20070168809 - Kiryu; Naoki ;   et al.
2007-07-19
Systems and methods for LBIST testing using isolatable scan chains
App 20070130489 - Kiryu; Naoki ;   et al.
2007-06-07
Method and apparatus for detecting frequency lock in a system including a frequency synthesizer
App 20070071154 - Boerstler; David William ;   et al.
2007-03-29
Information handling system capable of detecting frequency lock of signals downstream from a signal synthesized by frequency synthesizer
App 20070071155 - Boerstler; David William ;   et al.
2007-03-29
Apparatus and method for using a single bank of eFuses to successively store testing data from multiple stages of testing
App 20060294440 - Riley; Mack Wayne
2006-12-28
Method to gate off PLLS in a deep power saving state without separate clock distribution for power management logic
App 20060119445 - Riley; Mack Wayne ;   et al.
2006-06-08
Deep power saving by disabling clock distribution without separate clock distribution for power management logic
App 20060123261 - Riley; Mack Wayne ;   et al.
2006-06-08
Circuit to reduce transient current swings during mode transitions of high frequency/high power chips
App 20060093047 - Boerstler; David William ;   et al.
2006-05-04
Store scan data in trace arrays for on-board software access
App 20060080583 - Liberty; John Samuel ;   et al.
2006-04-13
Circuit to reduce power supply fluctuations in high frequency/ high power circuits
App 20060069929 - Boerstler; David William ;   et al.
2006-03-30
Dynamic frequency scaling sequence for multi-gigahertz microprocessors
App 20060053348 - Chelstrom; Nathan ;   et al.
2006-03-09

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