Riley; Deborah J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Riley; Deborah J..The latest application filed is for "embedded sige process for multi-threshold pmos transistors".

Company Profile

0.20.21

Riley; Deborah J. - Murphy TX
Riley; Deborah J. - Richardson TX
Riley, Deborah J - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
NPN heterojunction bipolar transistor in CMOS flow Grant 11,417,646 - Mehrotra , et al. August 16, 2	2022-08-16
Embedded Sige Process For Multi-threshold Pmos Transistors App 20180308977 - CHOI; Younsung ; et al.	2018-10-25
Embedded SiGe process for multi-threshold PMOS transistors Grant 10,026,837 - Choi , et al. July 17, 2	2018-07-17
Embedded Sige Process For Multi-threshold Pmos Transistors App 20170069755 - CHOI; Younsung ; et al.	2017-03-09
Npn Heterojunction Bipolar Transistor In Cmos Flow App 20160284691 - MEHROTRA; Manoj ; et al.	2016-09-29
NPN heterojunction bipolar transistor in CMOS flow Grant 9,385,117 - Mehrotra , et al. July 5, 2	2016-07-05
Npn Heterojunction Bipolar Transistor In Cmos Flow App 20150187755 - MEHROTRA; Manoj ; et al.	2015-07-02
ZTCR poly resistor in replacement gate flow Grant 8,927,385 - Nandakumar , et al. January 6, 2	2015-01-06
Strain-engineered MOSFETs having rimmed source-drain recesses Grant 8,877,581 - Jain , et al. November 4, 2	2014-11-04
Ztcr Poly Resistor In Replacement Gate Flow App 20140167182 - Nandakumar; Mahalingam ; et al.	2014-06-19
Method of forming a CMOS device with a stressed-channel NMOS transistor and a strained-channel PMOS transistor Grant 8,691,644 - Song , et al. April 8, 2	2014-04-08
Method of Forming a CMOS Device with a Stressed-Channel NMOS Transistor and a Strained-Channel PMOS Transistor App 20140011340 - Song; Seung-Chul ; et al.	2014-01-09
Silicide method Grant 8,470,707 - Xiong , et al. June 25, 2	2013-06-25
Improved Silicide Method App 20120108027 - Xiong; Weize ; et al.	2012-05-03
Nitride removal while protecting semiconductor surfaces for forming shallow junctions Grant 8,043,921 - Kirkpatrick , et al. October 25, 2	2011-10-25
Strain-engineered Mosfets Having Rimmed Source-drain Recesses App 20110042753 - Jain; Amitabh ; et al.	2011-02-24
Nitride Removal While Protecting Semiconductor Surfaces For Forming Shallow Junctions App 20100248440 - Kirkpatrick; Brian K. ; et al.	2010-09-30
Post High-k Dielectric/metal Gate Clean App 20100167519 - KIRKPATRICK; BRIAN K. ; et al.	2010-07-01
Post high-k dielectric/metal gate clean Grant 7,732,284 - Kirkpatrick , et al. June 8, 2	2010-06-08
Ic Formed With Densified Chemical Oxide Layer App 20100032813 - Riley; Deborah J. ; et al.	2010-02-11
Method for manufacturing a semiconductor device having improved across chip implant uniformity Grant 7,569,464 - Kirmse , et al. August 4, 2	2009-08-04
Differential offset spacer Grant 7,537,988 - Ekbote , et al. May 26, 2	2009-05-26
Differential Offset Spacer App 20090098695 - Ekbote; Shashank ; et al.	2009-04-16
Multi-step process for patterning a metal gate electrode Grant 7,422,969 - Rotondaro , et al. September 9, 2	2008-09-09
Method For Manufacturing A Semiconductor Device Having Improved Across Chip Implant Uniformity App 20080153273 - Kirmse; Karen H.R. ; et al.	2008-06-26
Protection of silicon from phosphoric acid using thick chemical oxide Grant 7,384,869 - Riley , et al. June 10, 2	2008-06-10
Silicon recess improvement through improved post implant resist removal and cleans Grant 7,371,691 - Hall , et al. May 13, 2	2008-05-13
Multi-step process for patterning a metal gate electrode Grant 7,323,403 - Rotondaro , et al. January 29, 2	2008-01-29
Multi-Step Process for Patterning a Metal Gate Electrode App 20080020558 - Rotondaro; Antonio L.P. ; et al.	2008-01-24
Treatment of silicon prior to nickel silicide formation Grant 7,132,365 - Crank , et al. November 7, 2	2006-11-07
Protection of silicon from phosphoric acid using thick chemical oxide App 20060228904 - Riley; Deborah J. ; et al.	2006-10-12
Semiconductor device having optimized shallow junction geometries and method for fabrication thereof Grant 7,098,099 - Hornung , et al. August 29, 2	2006-08-29
Semiconductor device having optimized shallow junction geometries and method for fabrication thereof App 20060189066 - Hornung; Brian E. ; et al.	2006-08-24
Multi-step process for patterning a metal gate electrode App 20060115972 - Rotondaro; Antonio L.P. ; et al.	2006-06-01
Treatment of silicon prior to nickel silicide formation App 20060035463 - Crank; Sue Ellen ; et al.	2006-02-16
Silicon recess improvement through improved post implant resist removal and cleans App 20060024972 - Hall; Lindsey H. ; et al.	2006-02-02
Control Of Transistor Performance Through Adjustment Of Spacer Oxide Profile With A Wet Etch App 20020119647 - Riley, Deborah J ; et al.	2002-08-29

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